Efficient generalized tensor product codes encoding schemes

US10333554B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10333554-B2
Application numberUS-201715639475-A
CountryUS
Kind codeB2
Filing dateJun 30, 2017
Priority dateJun 30, 2017
Publication dateJun 25, 2019
Grant dateJun 25, 2019

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

A method for generating a binary GTP codeword, comprised of N structure stages and each stage comprises at least one BCH codeword with error correction capability greater than a prior stage and smaller than a next stage, includes: receiving a syndrome vector s of a new stage 0 binary BCH codeword y over a field GF(2 m ) that comprises Δt syndromes of length m bits, wherein the syndrome vector s comprises l-th Reed-Solomon (RS) symbols of Δt RS codewords whose information symbols are delta syndromes of all BCH codewords from stage 0 until stage n−1; and multiplying s by a right submatrix Ũ of a matrix U, wherein U is an inverse of a parity matrix of an BCH code defined by t n , wherein the new binary BCH codeword is y =Ũ· s .

First claim

Opening claim text (preview).

What is claimed is: 1. A computer implemented method for generating a binary Generalized Tensor Product (GTP) codeword, comprised of N structure stages wherein N is an integer greater than 1 and each stage is comprised of at least one BCH codeword with error correction capability greater than a prior stage and smaller than a next stage, the method executed by the computer comprising the steps of: receiving new stage 0 binary BCH codeword y over a field GF(2 m ) from a communication channel; receiving a syndrome vector s of the new stage 0 binary BCH codeword y that comprises Δt syndromes of length m bits, wherein Δt=t n −t 0 , t 0 is the error correction capability of the stage 0 BCH codeword, t n is an error correction capability of a stage n BCH codeword to which a new binary BCH codeword y will be added, wherein the syndrome vector s comprises l-th Reed-Solomon (RS) symbols of Δt RS codewords whose information symbols are delta syndromes of all BCH codewords from stage 0 until stage n−1, wherein l indexes the BCH codeword to which y will be added; and multiplying s by a right submatrix Ũ of a matrix U, wherein U is an inverse of a parity matrix of an BCH code defined by t n , wherein the submatrix Ũ is of size mt 0 ×mΔt, wherein the new binary BCH codeword is y =Ũ· s . 2. The method of claim 1 , wherein multiplying s by right submatrix Ũ of matrix U comprises multiplying each component of the syndrome vector s by a component of submatrix Ũ by a binary logic function in a single hardware cycle to yield a component product, wherein submatrix Ũ is calculated before receiving syndrome vector s of new binary BCH codeword y , and multiplexing the component products into a single output that represents the new binary BCH codeword y . 3. The method of claim 2 , wherein the syndrome vector s is demultiplexed into separate Ũ matrices. 4. The method of claim 1 , wherein multiplying s by right submatrix Ũ of matrix U further comprises: multiplying each component of the syndrome vector s by a component of reduced submatrix Ũ′ by a binary logic function in a single hardware cycle to yield a component product, wherein reduced submatrix defined by Ũ′(x)=Ũ(x)/g 0 (x), wherein columns of submatrices Ũ′ and Ũ are represented as polynomials and each column of Ũ′(x) is the column of Ũ(x) divided by g 0 (x), are calculated before receiving syndrome vector s of new binary BCH codeword y ; multiplexing the component products into a temporary output; and convolving the temporary output with a common multiplier g 0 (x) to yield the single output that represents the new binary BCH codeword y , wherein g 0 (x) is a common multiplier of all columns of submatrix Ũ represented as polynomials and is calculated before receiving syndrome vector s of new binary BCH codeword y . 5. The method of claim 4 , wherein the syndrome vector s is demultiplexed into separate Ũ′ matrices. 6. The method of claim 4 , wherein convolving the temporary output with a common multiplier g 0 (x) is performed over multiple clock cycles. 7. The method of claim 1 , wherein multiplying s by a right submatrix Ũ of a matrix U further comprises: calculating a polynomial h j (x) by multiplying syndrome vector s by a matrix H j formed by concatenating the m polynomials h j,l as columns, wherein polynomials h j , l ⁡ ( x ) = U _ mj + l ′ ⁡ ( x ) / M j ⁡ ( x ) ⁢ ⁢ and ⁢ ⁢ M j ⁡ ( x ) = ∏ i = t 0 + 1 i ≠ j + t 0 + 1 t 1 ⁢ ⁢ m i ⁡ ( x ) m i (x) wherein m i (x) is an i-th minimal polynomial of the BCH code C 1 with correction capability of t 1 and is calculated before receiving syndrome vector s of new binary BCH codeword y ; multiplying h j (x) by M j (x), and summing over j=0 to Δt−1; multiplexing the sums of the products h j (x)×M j (x) into a temporary output; and convolving the temporary output with a common multiplier g 0 (x) to yield the single output that represents the new binary BCH codeword y , wherein g 0 (x) is a common multiplier of all columns of submatrix Ũ represented as polynomials and is calculated before receiving syndrome vector s of new binary BCH codeword y . 8. The method of claim 7 , wherein the syndrome vector s is demultiplexed into separate sets of H j and M j . 9. The method of claim 7 , wherein convolving the temporary output with a common multiplier g 0 (x) is performed over multiple clock cycles. 10. A computer processor configured to execute a program of instructions to perform the method steps generating a binary Generalized Tensor Product (GTP) codeword, comprised of N structure st

Assignees

Inventors

Classifications

  • Product codes · CPC title

  • Reed-Solomon codes · CPC title

  • H03M13/152Primary

    Bose-Chaudhuri-Hocquenghem [BCH] codes · CPC title

  • H03M13/616Primary

    Matrix operations, especially for generator matrices or check matrices, e.g. column or row permutations · CPC title

  • Polynomial operations, e.g. operations related to generator polynomials or parity-check polynomials · CPC title

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US10333554B2 cover?
A method for generating a binary GTP codeword, comprised of N structure stages and each stage comprises at least one BCH codeword with error correction capability greater than a prior stage and smaller than a next stage, includes: receiving a syndrome vector s of a new stage 0 binary BCH codeword y over a field GF(2 m ) that comprises Δt syndromes of length m bits, wherein the syndrome vect…
Who is the assignee on this patent?
Samsung Electronics Co Ltd
What technology area does this patent fall under?
Primary CPC classification H03M13/152. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jun 25 2019 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).