Scalable periphery tunable matching power amplifier

Patent metadata

Field	Value
Publication number	US-10333471-B2
Application number	US-201715827984-A
Country	US
Kind code	B2
Filing date	Nov 30, 2017
Priority date	Mar 12, 2013
Publication date	Jun 25, 2019
Grant date	Jun 25, 2019

Abstract

A scalable periphery tunable matching power amplifier is presented. Varying power levels can be accommodated by selectively activating or deactivating unit cells of which the scalable periphery tunable matching power amplifier is comprised. Tunable matching allows individual unit cells to see a constant output impedance, reducing need for transforming a low impedance up to a system impedance and attendant power loss. The scalable periphery tunable matching power amplifier can also be tuned for different operating conditions such as different frequencies of operation or different modes.

First claim

The invention claimed is:

1. An amplification circuit, comprising:
one or more amplifiers, wherein each amplifier of the one or more amplifiers comprises:
a stack of a plurality of transistors, and
one or more gate capacitors connected to respective one or more transistors of the plurality of transistors;

an output tunable matching network operatively connected to an output of the amplification circuit, wherein the tunable matching network is configured to adjust an output load impedance seen by the output of the amplification circuit;

wherein, in each amplifier:
an input transistor of the plurality of transistors of each of the amplifiers is configured to receive an input signal;
the one or more gate capacitors are connected between one or more gates of the respective one or more transistors and a reference ground with the exception of the input transistor;
a non-bypassing gate capacitor of the one or more gate capacitors is configured to allow a gate voltage of a respective transistor of the plurality of transistors to vary along with a radio frequency (RF) voltage at a drain of the respective transistor.

2. The amplification circuit of claim 1 , wherein the tunable matching network comprises:
one or more tunable reactive elements connected between the output of the amplification circuit and the output load; and
a tunable matching control circuit configured to tune the one or more tunable reactive elements to adjust the output load impedance seen by the output of the amplification circuit.

3. The amplification circuit of claim 1 , wherein the tunable matching network comprises:
a first set of one or more tunable reactive elements placed in series between the output of the amplification circuit and the output load impedance;
a second set of one or more tunable reactive elements placed in parallel with the output load impedance, and
a tunable matching control circuitry configured to tune the first set of the one or more tunable reactive elements and the second set of the one or more tunable reactive elements, thus adjusting the output load impedance seen by the output of the amplification circuit.

4. The amplification circuit of claim 1 , wherein the output tunable matching network comprises a plurality of tunable matching networks arranged in one or more of a: a) π-configuration, b) t-configuration, and c) cascade configuration, so as to achieve a desired bandwidth and/or quality factor.

5. The amplification circuit of claim 3 , wherein the one or more tunable reactive elements comprise one or more of: a) one or more digital tuning capacitors, and b) one or more digital tuning inductors.

6. The amplification circuit of claim 1 , wherein the output tunable matching network comprises one or more switches, the one or more switches being configured to adjust the output load impedance seen by the output of the amplification circuit.

7. The amplification circuit of claim 5 , wherein the one or more amplifiers and one or more of: a) the output tunable matching network in entirety or in part, and b) the tunable matching control circuitry in entirety or in part, are monolithically integrated.

8. The amplification circuit of claim 1 , wherein the output tunable matching network comprises a first inductor and a first capacitor, wherein the first inductor connects the output of the amplification circuit to the output load and the first capacitor is placed in parallel to the output load.

9. The amplification circuit of claim 8 , wherein the first inductor is a digitally tunable inductor and/or the first capacitor is a digitally tunable capacitor.

10. The amplification circuit of claim 1 , further comprising a harmonic termination network connected to the output of the amplification circuit.

11. The amplification circuit of claim 10 , wherein the harmonic termination network comprises one or more tunable reactive elements.

12. The amplification circuit of claim 11 , wherein the one or more tunable reactive elements are connected in one of a) series between the output of the amplification circuit and the output load or b) in parallel at the output of the amplification circuit or a combination thereof.

13. The amplification circuit of claim 9 , further comprising a harmonic terminating circuit connected to the output of the amplifier.

14. The amplification circuit of claim 13 , wherein the harmonic terminating circuit comprises a digitally tunable inductor and/or a digitally tunable capacitor connected in one of a) series or b) parallel to each other.

15. The amplification circuit of claim 14 , wherein the one or more amplifiers and one or more of: a) the output tunable matching network in entirety or in part, b) the tunable matching control circuitry in entirety or in part, or c) the harmonic termination network in entirety or in part are monolithically integrated.

16. The amplification circuit of claim 1 , further comprising an amplifier control circuitry configured to selectively activate or deactivate the one or more amplifiers.

17. The amplification circuit of claim 1 , further comprising an input tunable matching network operatively connected to an input of the amplification circuit, wherein an impedance of the input tunable matching network is configured to adjust relative to an input impedance of the input of the amplification circuit.

18. The amplification circuit of claim 10 , further comprising an input tunable matching network operatively connected to an input of the amplification circuit, wherein an impedance of the input tunable matching network is configured to adjust relative to an input impedance of the input of the amplification circuit.

19. The amplification circuit of claim 18 , wherein the one or more amplifiers and one or more of: a) the output tunable matching network in entirety or in part, b) the tunable matching control circuitry in entirety or in part, c) the harmonic termination network or d) the input tunable matching network in entirety or in part are monolithically integrated.

20. An amplification circuit comprising:
two or more amplifiers connected in parallel with each other and adapted to be selectively activated or deactivated, wherein each amplifier comprises a stack of a plurality of transistors;
an amplifier control circuitry configured to selectively activate or deactivate the one two or more amplifiers;
an output tunable matching comprising:
a first inductor, a second inductor, a first capacitor and a second capacitor
wherein:
the first inductor and the second inductor are connected to each other at a middle node and are placed in series between the output of the amplification circuit and the output load impedance;
the first capacitor connects the middle node to ground; the second capacitor is connected in parallel with the output load, and at least one of the first and second capacitors is a digitally tunable capacitor; and

wherein an input transistor of the plurality of transistors of each of the amplifiers is configured to receive an input signal of amplification circuit.

21. The amplification circuit of claim 20 , further comprising a harmonic termination circuit connected to the output of amplification circuit, the harmonic termination circuit comprising a series or parallel arrangement of an inductor and a digitally tunable capacitor.

22. The amplification circuit of claim 20 , further comprising one or more gate capacitors connected to respective one or more transistors of the plurality of transistors, wherein in eac

Assignees

• Psemi Corp

Inventors

• Nobbe Dan Willaim
• Halchin David
• Dykstra Jeffrey A
• Gaynor Michael P
• Kovac David
• Mekechuk Kelly Michael
• Kaatz Gary Frederick
• Olson Chris

Classifications

• H03F2200/222

  A circuit being added at the input of an amplifier to adapt the input impedance of the amplifier · CPC title

• H03F1/0261

  with control of the polarisation voltage or current, e.g. gliding Class A · CPC title

• H03F3/2176

  Class E amplifiers · CPC title

• H03F3/193

  with field-effect devices (H03F3/195 takes precedence) · CPC title

• H03F2200/411

  the output amplifying stage of an amplifier comprising two power stages · CPC title