Replacement metal gate stack for diffusion prevention

Patent metadata

Field	Value
Publication number	US-10332971-B2
Application number	US-201715826346-A
Country	US
Kind code	B2
Filing date	Nov 29, 2017
Priority date	Mar 6, 2014
Publication date	Jun 25, 2019
Grant date	Jun 25, 2019

Abstract

A method of forming a semiconductor structure includes depositing a gate dielectric layer lining a recess of a gate structure formed on a substrate with a first portion of the gate dielectric layer covering sidewalls of the recess and a second portion of the gate dielectric layer covering a bottom of the recess. A protective layer is deposited above the gate dielectric layer and then recessed selectively to the gate dielectric layer so that a top surface of the protective layer is below of the recess. The first portion of the gate dielectric layer is recessed until a top of the first portion of the gate dielectric layer is approximately coplanar with the top surface of the protective layer. The protective layer is removed and a conductive barrier is deposited above the recessed first portion of the gate dielectric layer to cut a diffusion path to the gate dielectric layer.

First claim

The invention claimed is:

1. A semiconductor structure comprising:
a gate structure formed above a substrate and contacting a sidewall of a gate spacer, the gate structure comprising:
a metal gate above a conductive barrier that is in direct physical contact with an upper portion of the gate spacer, wherein the conductive barrier, the gate spacer, and the metal gate have topmost surfaces that are coplanar with each other;
a gate dielectric layer below the conductive barrier, wherein the gate dielectric layer is U-Shaped having a topmost surface that is entirely beneath the topmost surfaces of each of the conductive barrier, the gate spacer, and the metal gate and wherein an outer vertical sidewall of the gate dielectric layer is in direct physical contact with a lower portion of the gate spacer; and
a capping layer above the gate structure and located directly on the topmost surface of each of the gate spacer, the conductive barrier and the metal gate, wherein the conductive barrier separates the capping layer from the gate dielectric layer.

2. The semiconductor structure of claim 1 , wherein the gate structure comprises a length less than 20 nm.

3. The semiconductor structure of claim 1 , wherein the conductive barrier comprises an n-type workfunction metal.

4. The semiconductor structure of claim 1 , wherein the gate dielectric layer comprises a high-k dielectric material.

5. The semiconductor structure of claim 1 , wherein the gate dielectric layer has a vertical portion and a horizontal portion, the vertical portion of the gate dielectric layer having a height less than a height of the metal gate measured from a top surface of the substrate.

6. The semiconductor structure of claim 5 , wherein the height of the vertical portion of the gate dielectric layer is within a range from 1 nm to 100 nm.

7. The semiconductor structure of claim 5 , wherein the vertical portion of the gate dielectric layer comprises a first vertical portion and a second vertical portion, and wherein upper surfaces of the first vertical portion and the second vertical portion of the gate dielectric layer are coplanar to each other.

8. The semiconductor structure of claim 5 , wherein a topmost surface of the horizontal portion of the gate dielectric layer directly contacts a bottommost surface of the conductive barrier.

9. The semiconductor structure of claim 1 , wherein the substrate is a semiconductor fin.

10. The semiconductor structure of claim 1 , wherein the conductive barrier is composed of Zr, W, Ta, Hf, Ti, Al, Ru, Pa, a metal oxide, a metal carbide, a metal nitride, a transition metal aluminide, or any combination thereof.

11. The semiconductor structure of claim 10 , wherein the conductive barrier is composed of Ti 3 Al, ZrAl, TaC, TiC, TaMgC, TiN or TiC.

12. The semiconductor structure of claim 1 , wherein the metal gate is composed of a metal having a lower resistivity than the conductive barrier.

13. The semiconductor structure of claim 1 , further comprising an interlayer dielectric material surrounding at least an upper portion of the gate structure.

14. The semiconductor structure of claim 1 , wherein the conductive barrier covers the entirety of the U-shaped gate dielectric material layer.

Assignees

• IBM

Inventors

• Ando Takashi
• Faltermeier Johnathan E
• Fan Su Chen
• Kanakasabapathy Sivananda K
• Ok Injo
• Yamashita Tenko

Classifications

• H10D64/01318

  the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314) · CPC title

• H01L29/42376

  Electricity · mapped topic

• H01L21/845

  Electricity · mapped topic

• H01L21/823456

  Electricity · mapped topic

• H01L29/517

  Electricity · mapped topic