Semiconductor device comprising work function metal pattern in boundry region and method for fabricating the same

Patent metadata

Field	Value
Publication number	US-10332894-B2
Application number	US-201715828934-A
Country	US
Kind code	B2
Filing date	Dec 1, 2017
Priority date	Feb 8, 2017
Publication date	Jun 25, 2019
Grant date	Jun 25, 2019

Abstract

A semiconductor device and method for fabricating the same are provided. The semiconductor device includes a substrate including a cell region, a core region, and a boundary region between the cell region and the core region, a boundary element isolation layer in the boundary region of the substrate to separate the cell region from the core region, a high-k dielectric layer on at least a part of the boundary element isolation layer and the core region of the substrate, a first work function metal pattern comprising a first extension overlapping the boundary element isolation layer on the high-k dielectric layer, and a second work function metal pattern comprising a second extension overlapping the boundary element isolation layer on the first work function metal pattern, wherein a first length of the first extension is different from a second length of the second extension.

First claim

What is claimed is:

1. A semiconductor device comprising:
a substrate including a cell region, a core region, and a boundary region between the cell region and the core region;
a boundary element isolation layer in the substrate of the boundary region, the boundary element isolation layer separating the cell region from the core region;
a high-k dielectric layer on at least a part of the boundary element isolation layer and the substrate of the core region;
a first work function metal pattern including a first extension overlapping the boundary element isolation layer, the first work function metal pattern being on the high-k dielectric layer; and
a second work function metal pattern including a second extension overlapping the boundary element isolation layer, at least a portion of the second work function metal pattern being on the first work function metal pattern and an end of the second work function metal pattern extending in a direction from the core region towards the cell region and overlapping the boundary element isolation layer,
wherein a first length of the first extension extending in a direction from the core region toward the cell region is different from a second length of the second extension extending in the direction from the core region toward the cell region.

2. The semiconductor device of claim 1 , wherein the first length is shorter than the second length.

3. The semiconductor device of claim 2 , wherein
the high-k dielectric layer includes a third extension which overlaps the boundary element isolation layer, and
a third length of the third extension extending in the direction from the core region toward the cell region is substantially the same as the second length.

4. The semiconductor device of claim 2 , wherein the boundary element isolation layer includes a recess adjacent to the second extension.

5. The semiconductor device of claim 1 , wherein the first length is longer than the second length.

6. The semiconductor device of claim 5 , wherein
the high-k dielectric layer includes a third extension overlapping the boundary element isolation layer, and
a third length of the third extension extending in the direction from the core region toward the cell region is substantially the same as the first length.

7. The semiconductor device of claim 5 , wherein the boundary element isolation layer includes a recess adjacent to the first extension.

8. The semiconductor device of claim 1 , wherein
the core region comprises first and second regions,
the first work function metal pattern is on the high-k dielectric layer of the first region, and is not on the substrate of the second region, and
the second work function metal pattern is on the first work function metal pattern of the first region, and is on the high-k dielectric layer of the second region.

9. The semiconductor device of claim 8 , wherein
the first work function metal pattern includes at least one of tungsten (W), tantalum (Ta), aluminum (Al), ruthenium (Ru), platinum (Pt), titanium nitride (TiN), tantalum nitride (TaN), titanium carbide (TiC), and tantalum carbide (TaC), and
the second work function metal pattern includes at least one of lanthanum (La), tantalum (Ta), tantalum nitride (TaN), niobium (Nb) and titanium nitride (TiN).

10. A semiconductor device comprising:
a substrate including a cell region, a core region, and a boundary region disposed between the cell region and the core region;
a boundary element isolation layer in the boundary region of the substrate to separate the cell region from the core region;
a high-k dielectric layer on at least a part of the boundary element isolation layer and the core region of the substrate;
a first work function metal pattern including a first extension overlapping the boundary element isolation layer on the substrate; and
a second work function metal pattern including a second extension overlapping the boundary element isolation layer, at least a portion of the second work function metal pattern being on the first work function metal pattern,
wherein the boundary element isolation layer includes a recess, and
the recess does not overlap the first and second extensions, and is adjacent to at least one of the first and second extensions.

11. The semiconductor device of claim 10 , wherein a first length of the first extension extending in a direction from the core region toward the cell region is substantially equal to a second length of the second extension extending in the direction from the core region toward the cell region.

12. The semiconductor device of claim 11 , wherein
the high-k dielectric layer includes a third extension which overlaps the boundary element isolation layer, and
a third length of the third extension extending in the direction from the core region toward the cell region is substantially equal to the first and second lengths.

13. The semiconductor device of claim 10 , wherein
the second extension extends further in a direction from the core region toward the cell region than the first extension, and
the recess is adjacent to the second extension.

14. The semiconductor device of claim 10 , wherein
the first extension extends further in a direction from the core region toward the cell region than the second extension, and
the recess is adjacent to the first extension.

15. The semiconductor device of claim 10 , wherein
the core region comprises first and second regions,
the first work function metal pattern is on the first region of the substrate, and is not disposed on the second region of the substrate, and
the second work function metal pattern is on the first work function metal pattern of the first region and the second region of the substrate.

16. A semiconductor device comprising:
a cell region in a substrate;
an element isolation layer around the cell region;
a high-k dielectric layer extending onto a portion of the element isolation layer;
a first work function metal pattern extending a first length onto the element isolation layer, the first work function metal pattern being on the high-k dielectric layer; and
a second work function metal pattern extending a second length onto the element isolation layer, at least a portion of the second work function metal pattern being on the first work function metal pattern, the second length being different from the first length, wherein
the element isolation layer includes a recess, and
the recess does not overlap the first and second work function metal patterns.

17. The semiconductor device of claim 16 , wherein the recess is between the cell region and both of the first work function metal pattern and the second work function metal pattern.

18. The semiconductor device of claim 17 , wherein
the first length is greater than the second length, and
the recess is adjacent to the first work function metal pattern.

19. The semiconductor device of claim 17 , wherein
the second length is greater than the first length, and
the recess is adjacent to the second work function metal pattern.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Jung Ki Wook
• Kim Dong Oh
• Park Seok Han
• Yoon Chan Sic
• Lee Ki Seok
• Lee Ho In
• Jang Ju Yeon
• Park Je Min
• Hong Jin Woo

Classifications

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H10W20/031

  of conductive parts of the interconnections · CPC title

• H10W20/076

  in via holes or trenches · CPC title

• H10W20/074 Primary

  of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers · CPC title

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title