Segmented digital-to-analog converter (DAC)

Patent metadata

Field	Value
Publication number	US-10326469-B1
Application number	US-201815936034-A
Country	US
Kind code	B1
Filing date	Mar 26, 2018
Priority date	Mar 26, 2018
Publication date	Jun 18, 2019
Grant date	Jun 18, 2019

Abstract

Certain aspects of the present disclosure provide apparatus and techniques for segmenting a digital input signal for digital-to-analog conversion. For example, certain aspects provide a segmentation circuit for generating digital signal segments for a digital-to-analog converter. The segmentation circuit generally includes a modulo function logic circuit configured to generate a modulo output signal based on a digital input signal and a divisor input signal and a modulo range extension logic circuit configured to selectively direct the modulo output signal or the divisor input signal to an output of the segmentation circuit. In certain aspects, the output of the segmentation circuit may be used by the digital-to-analog converter to generate an analog signal based on the digital input signal.

First claim

What is claimed is:

1. A segmentation circuit for generating digital signal segments for a digital-to-analog converter, comprising:
a modulo function logic circuit configured to generate a modulo output signal based on a digital input signal and a divisor input signal; and
a modulo range extension logic circuit configured to selectively direct the modulo output signal or the divisor input signal to an output of the segmentation circuit, the output of the segmentation circuit to be used by the digital-to-analog converter to generate an analog signal based on the digital input signal.

2. The segmentation circuit of claim 1 , wherein the modulo range extension logic circuit comprises a comparison circuit configured to compare the modulo output signal to zero, the modulo range extension logic circuit being configured to selectively direct the modulo output signal or the divisor input signal to the output of the segmentation circuit based on the comparison.

3. The segmentation circuit of claim 2 , wherein:
the modulo range extension logic circuit further comprises a first switch;
the modulo range extension logic circuit is configured to selectively direct the divisor input signal to the output of the segmentation circuit via the first switch; and
the first switch comprises a first input selectively coupled to a node configured to receive the divisor input signal and a second input selectively coupled to an output of the modulo function logic circuit.

4. The segmentation circuit of claim 3 , wherein:
the modulo range extension logic circuit further comprises a second switch;
the first input of the first switch is selectively coupled to the node for receiving the divisor input signal via the second switch; and
the second switch comprises a first input coupled to the node for receiving the divisor input signal and a second input coupled to a node having a constant value of zero, the second switch being configured to direct the first input or the second input of the second switch to the first input of the first switch based on the comparison.

5. The segmentation circuit of claim 4 , wherein the modulo range extension logic circuit further comprises a control circuit configured to control the second switch such that the second switch is configured to direct the divisor input signal to the first input of the first switch at most once across two consecutive sampling periods of the digital-to-analog converter.

6. The segmentation circuit of claim 5 , wherein the control circuit has an output coupled to a control input of the second switch, the control circuit comprising:
another modulo function logic circuit having a divisor input coupled to a node having a constant value of two and an output coupled to the output of the control circuit;
an adder having a first input coupled to an output of the comparison circuit and a second input coupled to an output of the other modulo function logic circuit; and
a delay element having an input coupled to an output of the adder and an output coupled to a dividend input of the other modulo function logic circuit.

7. The segmentation circuit of claim 1 , further comprising:
a subtraction circuit configured to subtract a value at a first input of the subtraction circuit from a value at a second input of the subtraction circuit, wherein the first input is coupled to a node configured to receive the divisor input signal and the second input is coupled to an output of the modulo function logic circuit; and
a switch having a first input coupled to an output of the subtraction circuit, a second input coupled to the output of the modulo function logic circuit, and an output selectively coupled to the output of the segmentation circuit.

8. The segmentation circuit of claim 7 , further comprising:
an integrator having an input coupled to the output of the segmentation circuit and having an output coupled to a control input of the switch.

9. The segmentation circuit of claim 1 , further comprising:
a subtraction circuit configured to subtract a value at a first input of the subtraction circuit from a value at a second input of the subtraction circuit, the first input being coupled to the output of the segmentation circuit and the second input being coupled to a node configured to receive the digital input signal; and
a divider circuit configured to divide a value at a first input of the divider circuit by a value at a second input of the divider circuit, the first input being coupled to an output of the subtraction circuit and the second input being coupled to a node configured to receive the divisor input signal, the output of the divider circuit being coupled to a remainder output of the segmentation circuit.

10. A plurality of segmentation circuits for generating the digital signal segments for the digital-to-analog converter, wherein the plurality of segmentation circuits includes the segmentation circuit of claim 9 and wherein the remainder output is coupled to an input of another segmentation circuit of the plurality of segmentation circuits.

11. A digital-to-analog converter comprising:
a segmentation circuit configured to receive a digital input signal to be converted to an analog signal and generate multiple digital signal segments based on the digital input signal;
at least one pulse-density modulation encoder and at least one pulse-width modulation encoder coupled to outputs of the segmentation circuit; and
a plurality of digital-to-analog converter elements, wherein the pulse-density modulation encoder and pulse-width modulation encoder are coupled to the digital-to-analog converter elements and are configured to generate encoded signals based on the multiple digital signal segments and to provide the encoded signals to the digital-to-analog converter elements, the digital-to-analog converter elements being configured to generate the analog signal.

12. The digital-to-analog converter of claim 11 , wherein the pulse-density modulation encoder and the pulse-width modulation encoder are selectively enabled to generate the encoded signals.

13. The digital-to-analog converter of claim 11 , wherein:
the at least one pulse-density modulation encoder comprises a plurality of pulse-density modulation encoders, each coupled to a different subset of elements of the plurality of digital-to-analog converter elements; and
the at least one pulse-width modulation encoder comprises a plurality of pulse-width modulation encoders, each coupled to the different subset of elements of the plurality of digital-to-analog converter elements.

14. The digital-to-analog converter of claim 13 , wherein gains corresponding to the digital-to-analog converter elements of each of the subsets are different from gains of digital-to-analog converter elements of other subsets of the plurality of digital-to-analog converter elements.

15. The digital-to-analog converter of claim 11 , wherein the pulse-density modulation encoder is configured to generate the encoded signals using dynamic element matching to reduce non-linear distortion associated with the analog signal.

16. The digital-to-analog converter of claim 11 , wherein the segmentation circuit comprises:
a modulo function logic circuit configured to generate a modulo output signal based on the digital input signal and a divisor input signal; and
a modulo range extension logic circuit configured to selectively direct the modulo output signal or the divisor input signal to an output of the segmentation circuit for providing a first segment of the digital signal segments.

17. The digital-to-analog converter of

Assignees

• Qualcomm Inc

Inventors

• Cope William

Classifications

• H03M7/3006

  Compensating for, or preventing of, undesired influence of physical parameters · CPC title

• H03M3/506 Primary

  the final digital/analogue converter being constituted by a pulse width modulator · CPC title

• H03M3/422

  having one quantiser only · CPC title

• H03M1/68

  with conversions of different sensitivity, i.e. one conversion relating to the more significant digital bits and another conversion to the less significant bits · CPC title

• H03M7/3033

  the modulator having a higher order loop filter in the feedforward path, e.g. with distributed feedforward inputs · CPC title