Phase combiner circuit

Patent metadata

Field	Value
Publication number	US-10326456-B2
Application number	US-201715495521-A
Country	US
Kind code	B2
Filing date	Apr 24, 2017
Priority date	Apr 24, 2017
Publication date	Jun 18, 2019
Grant date	Jun 18, 2019

Abstract

Methods and devices are discussed where a plurality of input signals having different phases are provided. From the input signals, a plurality of signal pairs are selected, and intermediate signals are generated based on the signal pairs. The intermediate signals are then combined.

First claim

What is claimed is:

1. A device comprising:
a signal generator configured to generate a plurality of signals having different phases;
a selection circuit configured to select a plurality of signal pairs from the plurality of signals; and
a phase combiner circuit comprising a logic gate and configured to generate a plurality of intermediate signals, each intermediate signal being based on one of the plurality of signal pairs such that a first signal of the respective signal pair determines rising edges of the respective intermediate signal and a second signal of the respective signal pair defines falling edges of the respective intermediate signal,
wherein the logic gate is configured to combine the plurality of intermediate signals to form an output signal.

2. The device of claim 1 , wherein rising edges of at least one intermediate signal of the plurality of intermediate signals correspond to rising edges of the first signal of the respective signal pair, and falling edges of the at least one intermediate signal correspond to rising edges of the second signal of the respective signal pair.

3. The device of claim 1 , wherein the logic gate comprises an OR gate.

4. The device of claim 1 , wherein the phase combiner circuit, for at least one of the signal pairs, comprises a flip-flop coupled to the selector circuit such that a first signal of the signal pair is provided to a first input of the flip-flop and a second signal of the signal pair is provided to a second input of the flip flop.

5. The device of claim 4 ,
wherein the flip-flop is a D flip-flop,
wherein the first input is a clock input, and
wherein the second input is a reset input.

6. The device of claim 5 , further comprising an inverter to provide the second signal to the reset input of the flip-flop.

7. The device of claim 5 , further comprising an inverter coupled between an output of the flip-flop and a data input of the flip-flop.

8. The device of claim 5 , wherein the device is configured to provide a value corresponding to a logic 1 to a data input of the flip-flop.

9. The device of claim 4 , further comprising a respective flip-flop for each of the signal pairs.

10. The device of claim 1 , wherein the signal generator comprises at least one of a delay locked loop, a delay chain, or a ring oscillator.

11. The device of claim 1 , wherein the selection circuit comprises a multiplexer.

12. The device of claim 1 , further comprising a frequency divider coupled to the output of the phase combiner circuit.

13. A device comprising:
a delay locked loop configured to provide a plurality of input signals having different phases based on a reference signal;
a multiplexer configured to select a plurality of pairs of signals from the plurality of input signals;
for each of the plurality of pairs of signals, a D flip-flop, wherein a clock input of the D flip-flop is configured to receive a first signal of the respective pair of signals and a reset input of the D flip-flop is configured to receive a second signal of the respective pair of signals via an inverter; and
an OR gate coupled to outputs of the D flip-flops.

14. A method comprising:
providing multiple input signals having different phases;
selecting a plurality of signal pairs from the multiple input signals;
forming a plurality of intermediate signals, each intermediate signal based on one of the plurality of signal pairs, wherein each intermediate signal is formed such that rising edges of the respective intermediate signals are based on a first signal of the respective signal pair and falling edges of the respective intermediate signal are based on the second signal of the respective signal pair; and
combining, by a logic gate, the intermediate signals to form an output signal.

15. The method of claim 14 , wherein forming the plurality of intermediate signals comprises forming the intermediate signals such that the rising edges of each intermediate signal correspond to rising edges of the first signal of the respective signal pair and falling edges of the intermediate signal correspond to rising edges of the second signal of the respective signal pair.

16. The method of claim 14 , further comprising frequency dividing the combined intermediate signals.

17. The method of claim 14 , wherein selecting the signal pairs of input signals comprises selecting the signal pairs to adjust a duty cycle.

18. The method of claim 14 , wherein the combined intermediate signal has a frequency corresponding to a frequency of each of the input signals multiplied by a number of selected signal pairs.

19. The device of claim 1 , wherein the combined intermediate signal has a frequency corresponding to a frequency of each of the input signals multiplied by a number of selected signal pairs.

20. The device of claim 1 , wherein the combined intermediate signal has a duty cycle based on a selection of the plurality of signal pairs by the selection circuit.

Assignees

• Infineon Technologies Ag

Inventors

• Grollitsch Werner

Classifications

• H03K5/00006 Primary

  Changing the frequency (modulating pulses H03K7/00; frequency dividers H03K21/00 - H03K29/00; additive or subtractive mixing of two pulse rates into one G06F7/605; pulse rate dividers G06F7/68) · CPC title

• H03L7/085 Primary

  concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal (H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00) · CPC title