Semiconductor device including insulating layers and method of forming the same

Patent metadata

Field	Value
Publication number	US-10325922-B2
Application number	US-201715816638-A
Country	US
Kind code	B2
Filing date	Nov 17, 2017
Priority date	May 31, 2017
Publication date	Jun 18, 2019
Grant date	Jun 18, 2019

Abstract

A semiconductor device includes a substrate, a stacked structure of insulating layers and gate electrodes alternately and repeatedly stacked on the substrate, and a pillar passing through the stacked-layer structure. The insulating layers include lower insulating layers, intermediate insulating layers disposed on the lower insulating layers, and upper insulating layers disposed on the intermediate insulating layers. The lower insulating layers have a hardness less than that of the intermediate insulating layers, and the upper insulating layers have a hardness greater than that of the intermediate insulating layers.

First claim

What is claimed is:

1. A semiconductor device comprising:
a substrate;
a stacked-layer structure having insulating layers and gate electrodes, the insulating layers alternately stacked with the gate electrodes on the substrate; and
a pillar passing through the stacked-layer structure,
wherein:
the insulating layers include a plurality of lower insulating layers, a plurality of intermediate insulating layers on the lower insulating layers, and a plurality of upper insulating layers on the plurality of intermediate insulating layers;
the plurality of lower insulating layers has a hardness lower than that of the plurality of intermediate insulating layers; and
the plurality of upper insulating layers has a hardness higher than that of the plurality of intermediate insulating layers.

2. The semiconductor device of claim 1 , wherein:
the hardness of the plurality of lower insulating layers is 1% to 15% lower than that of the plurality of the intermediate insulating layers; and
the hardness of the plurality of upper insulating layers is 1% to 15% higher than that of the plurality of the intermediate insulating layers.

3. The semiconductor device of claim 1 , wherein each of the lower insulating layers, the intermediate insulating layers, and the upper insulating layers comprises silicon oxide.

4. The semiconductor device of claim 1 , further comprising a plurality of shape control insulating layers interposed between a lower group of the intermediate insulating layers and an upper group of the intermediate insulating layers, between the plurality of intermediate insulating layers and the plurality of lower insulating layers, or between the plurality of upper insulating layers and the plurality of intermediate insulating layers,
wherein the plurality of shape control insulating layers have a hardness lower than that of the plurality of intermediate insulating layers.

5. The semiconductor device of claim 4 , wherein the plurality of shape control insulating layers have a hardness lower than that of the plurality of lower insulating layers.

6. The semiconductor device of claim 4 , wherein the hardness of the plurality of shape control insulating layers is 1% to 15% lower than that of the plurality of intermediate insulating layers.

7. The semiconductor device of claim 4 , wherein:
the pillar has a first width in a region in which the pillar passes through the plurality of intermediate insulating layers,
the pillar has a second width in a region in which the pillar passes through the shape control insulating layers, and
the second width is greater than the first width.

8. The semiconductor device of claim 4 , wherein the plurality of shape control insulating layers occupies a region of the device within a range of 0.3 times to 0.7 times a height of the stacked-layer structure.

9. A semiconductor device comprising:
a substrate in a cell region and a connection region of the device;
a stacked-layer structure in the cell region and having insulating layers and gate electrodes, the insulating layers alternately stacked with the gate electrodes on the substrate;
an insulating interlayer in the connection region and covering the stacked-layer structure in the connection region;
a cell pillar passing through the stacked-layer structure in the cell region; and
a dummy pillar passing through the insulating interlayer and the stacked-layer structure in the connection region,
wherein:
the insulating layers include a plurality of lower insulating layers, a plurality of intermediate insulating layers on the plurality of lower insulating layers, and a plurality of upper insulating layers on the plurality of intermediate insulating layers;
the plurality of lower insulating layers have a hardness lower than that of the plurality of intermediate insulating layers; and
the plurality of upper insulating layers have a hardness higher than that of the plurality of intermediate insulating layers.

10. The semiconductor device of claim 9 , wherein:
an upper end of the cell pillar has a first width;
the dummy pillar has a second width at substantially the same horizontal level as that where the upper end of the cell pillar has the first width; and
the first width is smaller than the second width.

11. The semiconductor device of claim 9 , wherein:
a lower end of the cell pillar has a third width;
the dummy pillar has a fourth width at substantially the same horizontal level as that where the lower end of the cell pillar has the third width; and
the third width is greater than the fourth width.

12. The semiconductor device of claim 9 , wherein:
an upper region of the cell pillar passes through the upper insulating layers;
an angle subtended by a side surface of the upper region of the cell pillar and a first line perpendicular to a surface of the substrate is smaller than an angle subtended by a side surface of the dummy pillar and a second line perpendicular to the surface of the substrate; and
the side surface of the upper region of the cell pillar intersects the first line at substantially the same horizontal level in the device as that at which the side surface of the dummy pillar intersects the second line.

13. The semiconductor device of claim 9 , wherein:
a lower region of the cell pillar passes through the lower insulating layers;
an angle subtended by a side surface of the lower region and a first line perpendicular to a surface of the substrate is smaller than an angle subtended by a side surface of the dummy pillar and a second line perpendicular to the surface of the substrate; and
the side surface of the lower region of the cell pillar intersects the first line at substantially the same horizontal level in the device as that at which the side surface of the dummy pillar intersects the second line.

14. The semiconductor device of claim 9 , further comprising a plurality of shape control insulating layers interposed between a lower group of the plurality of intermediate insulating layers and an upper group of the plurality of intermediate insulating layers, between the plurality of intermediate insulating layers and the plurality of lower insulating layers, or between the plurality of upper insulating layers and the plurality of intermediate insulating layers,
wherein the plurality of shape control insulating layers have a hardness lower than that of the plurality of intermediate insulating layers.

15. The semiconductor device of claim 14 , wherein:
the cell pillar has a fifth width in a region in which the cell pillar passes through the shape control insulating layers;
the dummy pillar has a sixth width at substantially the same horizontal level as that at which the cell pillar has the fifth width; and
the fifth width is greater than the sixth width.

16. The semiconductor device of claim 9 , wherein the insulating interlayer includes:
a first interlayer insulating layer having substantially the same hardness as the plurality of lower insulating layers;
a second interlayer insulating layer having substantially the same hardness as the plurality of intermediate insulating layers and disposed on the first interlayer insulating layer; and
a third interlayer insulating layer having substantially the same hardness as the plurality of upper insulating layers and disposed on the second interlayer insulating layer.

17. A semiconductor device comprising:
a substrate;
a stacked-layer structure having insulating layers and gate electrodes, the insulating layers alternately stacked with the gate electrodes on the substrate; and
a pillar passing th

Assignees

• Lim Yeong Dae
• Jung Seung Jae
• Bang Jin Young
• Kim Il Woo
• Jung Ho Gil
• Samsung Electronics Co Ltd

Inventors

• Lim Yeong Dae
• Jung Seung Jae
• Bang Jin Young
• Kim Il Woo
• Jung Ho Gil

Classifications

• H10P50/283

  by chemical means · CPC title

• H10P14/69433

  the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz · CPC title

• H10P14/69215

  the material being a silicon oxide, e.g. SiO2 · CPC title

• H10P14/6682

  the compound being a silane, e.g. disilane, methylsilane or chlorosilane · CPC title

• H10P14/6339

  deposition by cyclic CVD, e.g. ALD, ALE or pulsed CVD · CPC title