Wafer rigidity with reinforcement structure

Patent metadata

Field	Value
Publication number	US-10325862-B2
Application number	US-201715657666-A
Country	US
Kind code	B2
Filing date	Jul 24, 2017
Priority date	Jun 29, 2015
Publication date	Jun 18, 2019
Grant date	Jun 18, 2019

Abstract

Reinforcement structures used with a thinned wafer and methods of manufacture are provided. The method includes forming trenches or vias at least partially through a backside of a thinned wafer attached to a carrier wafer. The method further includes depositing material within the trenches or vias to form reinforcement structures on the backside of the thinned wafer. The method further includes removing excess material from a surface of the thinned wafer, which was deposited during the depositing of the material within the vias.

First claim

What is claimed:

1. A method comprising:
forming trenches or vias at least partially through a backside of a thinned wafer attached to a carrier wafer;
depositing material within the trenches or vias to form reinforcement structures on the backside of the thinned wafer; and
removing excess material from the backside of the thinned wafer, which was deposited during the depositing of the material within the trenches or vias,
wherein:
the reinforcement structures and thru-silicon-vias adjacent to the reinforcement structures are formed simultaneously by etching and deposition processes, and
a cross section of the trenches or vias is smaller than a cross section of the thru-silicon-vias.

2. The method of claim 1 , wherein the material includes depositing a liner material in the trenches or vias and the material is conductive material.

3. The method of claim 1 , further comprising:
lining the trenches or vias and the thru-silicon-vias with a dielectric material;
removing the dielectric material from a bottom surface of the trenches or vias and the thru-silicon-vias;
depositing a conductive material over the dielectric material in the trenches or vias and the thru-silicon-vias; and
removing excessive conductive material from the backside of the thinned wafer.

4. The method of claim 1 , further comprising:
lining the thru-silicon-vias with a dielectric material;
filling the trenches or vias with the dielectric material;
removing the dielectric material from a bottom surface of the thru-silicon-vias;
depositing a conductive material over the dielectric material in the thru-silicon-vias; and
removing excessive conductive material from the backside of the thinned wafer.

5. The method of claim 1 , wherein the reinforcement structures are formed by patterning of the material on the backside of the thinned wafer.

6. The method of claim 5 , wherein the reinforcement structures are patterned in a “T” shape, with a portion of the reinforcement structures formed in the trenches or vias and another portion of the reinforcement structures formed on the backside of the thinned wafer.

7. The method of claim 1 , wherein the reinforcement structures are formed in a grid pattern or honeycomb pattern on the backside of the thinned wafer.

8. The method of claim 1 , wherein the reinforcement structures are formed locally around thru-silicon-vias.

9. The method of claim 1 , wherein the reinforcement structures are a formed in an “I” shape.

10. The method of claim 9 , wherein fabricating the “I” shape reinforcement structures comprises:
depositing non-conformal material on sidewalls of the trenches or vias;
etching the thinned wafer through exposed portions from within the trenches or vias which were not covered by the non-conformal material, to form undercuts in the thinned wafer through the vias;
depositing the material in the trenches or vias and in the undercuts; and
patterning the material on the backside of the thinned wafer.

11. A method comprising:
etching trenches or vias partially through a backside of a thinned wafer;
etching thru-silicon-vias extending through the backside of the thinned wafer;
simultaneously depositing material within the thru-silicon-vias and within the trenches or vias, the material deposited within the trenches or vias forming reinforcement structures on the backside of the thinned wafer;
removing excess material from the backside of the thinned wafer, which was deposited during the depositing of the material within the trenches or vias and within the thru-silicon-vias;
lining the trenches or vias and the thru-silicon-vias with a dielectric material;
removing the dielectric material from a bottom surface of the trenches or vias and the thru-silicon-vias;
depositing the material over the dielectric material in the trenches or vias and over the dielectric material in the thru-silicon-vias, the material being a conductive material; and
removing excessive conductive material from the backside of the thinned wafer.

12. The method of claim 11 , wherein a cross section of the trenches or vias is smaller than a cross section of the thru-silicon vias.

13. The method of claim 11 , wherein the reinforcement structures are formed in a grid pattern or honeycomb pattern on the backside of the thinned wafer.

14. The method of claim 11 , wherein the reinforcement structures are formed locally around the thru-silicon-vias.

15. A method comprising:
etching trenches or vias partially through a backside of a thinned wafer;
etching thru-silicon-vias extending through the backside of the thinned wafer;
simultaneously depositing material within the thru-silicon-vias and within the trenches or vias, the material deposited within the trenches or vias forming reinforcement structures on the backside of the thinned wafer; and
removing excess material from the backside of the thinned wafer, which was deposited during the depositing of the material within the trenches or vias and within the thru-silicon-vias,
wherein the reinforcement structures are a formed in an “I” shape, comprises:
depositing non-conformal material on sidewalls of the trenches or vias;
etching the thinned wafer through exposed portions from within the trenches or vias which were not covered by the non-conformal material, to form undercuts in the thinned wafer through the vias;
depositing the material in the trenches or vias and in the undercuts; and
patterning the material on the backside of the thinned wafer.

Assignees

• Globalfoundries Inc

Inventors

• Filippi Ronald G
• Kaltalioglu Erdem
• Kim Andrew T
• Wang Ping-Chuan

Classifications

• H10W20/041

  the barrier, adhesion or liner layers being discontinuous · CPC title

• H10W20/023

  the interconnections being through-semiconductor vias · CPC title

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H10W42/121 Primary

  protecting against mechanical damage (H10W76/00, H10W74/00 take precedence) · CPC title

• H01L23/562 Primary

  Electricity · mapped topic