Semiconductor wafer and method for processing a semiconductor wafer

Patent metadata

Field	Value
Publication number	US-10325803-B2
Application number	US-201815969868-A
Country	US
Kind code	B2
Filing date	May 3, 2018
Priority date	May 30, 2014
Publication date	Jun 18, 2019
Grant date	Jun 18, 2019

Abstract

According to various embodiments, a semiconductor wafer may include: a semiconductor body including an integrated circuit structure; and at least one tetrahedral amorphous carbon layer formed at least one of over or in the integrated circuit structure, the at least one tetrahedral amorphous carbon layer may include a substance amount fraction of sp 3 -hybridized carbon of larger than approximately 0.4 and a substance amount fraction of hydrogen smaller than approximately 0.1.

First claim

What is claimed is:

1. A semiconductor wafer comprising:
a semiconductor body comprising an integrated circuit structure; and
at least one tetrahedral amorphous carbon layer formed at least one of over or in the integrated circuit structure, the at least one tetrahedral amorphous carbon layer comprising a substance amount fraction of sp 3 -hybridized carbon of larger than approximately 0.4 and a substance amount fraction of hydrogen smaller than approximately 0.1; wherein the at least one tetrahedral amorphous carbon layer is stable at a temperature of about 1000° C. or more.

2. The semiconductor wafer according to claim 1 ,
wherein the tetrahedral amorphous carbon layer is disposed between a first region of the integrated circuit structure and a second region of the integrated circuit structure.

3. The semiconductor wafer according to claim 1 ,
wherein the tetrahedral amorphous carbon layer is disposed between a first region of the integrated circuit structure and a second region of the integrated circuit structure to electrically isolate the first region from the second region of the integrated circuit structure.

4. The semiconductor wafer according to claim 1 ,
wherein the tetrahedral amorphous carbon layer connects at least a part of the integrated circuit structure to a heat sink structure to dissipate heat from the integrated circuit structure.

5. The semiconductor wafer according to claim 1 ,
wherein the tetrahedral amorphous carbon layer is doped with metal or a semi metal.

6. The semiconductor wafer according to claim 1 ,
further comprising at least one additional layer over the at least one tetrahedral amorphous carbon layer; wherein at least a portion of the at least one additional layer has been removed to where the at least one tetrahedral amorphous carbon layer is at least partially exposed through the at least one additional layer.

7. A method, comprising:
applying a high-power impulse magnetron sputtering process to form a tetrahedral amorphous carbon layer over a semiconductor wafer; and
subsequently carrying out a thermal treatment of the semiconductor wafer at a temperature of higher than about 400° C.;
forming at least one additional layer over the at least one tetrahedral amorphous carbon layer and performing a chemical mechanical polishing to at least partially remove the additional layer and at least partially expose the at least one tetrahedral amorphous carbon layer through the at least one additional layer.

8. The method according to claim 7 , further comprising:
forming an electronic structure at least one of over or in the semiconductor wafer.

9. The method according to claim 7 ,
wherein an average ion energy of the carbon ions sputtered in the high-power impulse magnetron sputtering is in the range from about 40 eV per ion to about 5 keV per ion.

10. The method according to claim 7 ,
wherein the high-power impulse magnetron sputtering process is configured such that carbon ions sputtered from a cathodic target precipitate at a surface of the semiconductor wafer.

11. The method according to claim 7 ,
wherein a negative bias voltage is applied to the semiconductor wafer during the high-power impulse magnetron sputtering.

12. The method according to claim 11 ,
wherein the negative bias voltage is an RF-voltage provided by an RF-power source.

13. The method according to claim 12 ,
wherein the negative bias voltage is in the range from about 20 V to about 140 V.

Assignees

• Infineon Technologies Ag

Inventors

• Kuenle Matthias
• Schmidt Gerhard
• Sporn Martin
• Kahn Markus
• Steinbrenner Juergen
• Joshi Ravi

Classifications

• H10P14/3406

  Carbon, e.g. diamond-like carbon · CPC title

• H10P14/22

  using physical deposition, e.g. vacuum deposition or sputtering · CPC title

• H10W10/011 Primary

  of isolation regions comprising dielectric materials · CPC title

• H10W10/10 Primary

  Isolation regions comprising dielectric materials · CPC title

• H10P14/3454

  Amorphous · CPC title