Handler bonding and debonding for semiconductor dies

US10325785B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10325785-B2
Application numberUS-201715855134-A
CountryUS
Kind codeB2
Filing dateDec 27, 2017
Priority dateDec 30, 2015
Publication dateJun 18, 2019
Grant dateJun 18, 2019

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Various embodiments process semiconductor devices. In one embodiment, a release layer is applied to a handler. The at least one singulated semiconductor device is bonded to the handler. The at least one singulated semiconductor device is packaged while it is bonded to the handler. The release layer is ablated by irradiating the release layer through the handler with a laser. The at least one singulated semiconductor device is removed from the transparent handler after the release layer has been ablated.

First claim

Opening claim text (preview).

What is claimed is: 1. A method for processing semiconductor devices, the method comprising: applying a release layer in contact with a handler; building semiconductor packaging components in contact with the release layer; bonding at least one singulated semiconductor device to the semiconductor packaging components; ablating the release layer by irradiating the release layer through the handler with a laser; and removing the at least one singulated semiconductor device from the handler after the release layer has been ablated. 2. The method of claim 1 , wherein the release layer comprises one or more additive materials, wherein the additive materials adjust a frequency of light absorption property of the release layer. 3. The method of claim 1 , wherein the handler is transparent. 4. The method of claim 1 , wherein the handler is one of: a handle wafer; a panel; and a roll of handler material. 5. The method of claim 1 , wherein the release layer absorbs a frequency of light radiated from the laser. 6. A system for processing semiconductor devices, the system comprising: memory; at least one processor operatively coupled to the memory; at least one control unit operatively coupled to the memory and the at least one processor, the control unit operating at least one semiconductor device processing component of the system to: apply a release layer in contact with a handler; build semiconductor packaging components in contact with the release layer; bond at least one singulated semiconductor device to the semiconductor packaging components; ablate the release layer by irradiating the release layer through the handler with a laser; and remove the at least one singulated semiconductor device from the handler after the release layer has been ablated. 7. The system of claim 6 , wherein the release layer comprises one or more additive materials, wherein the additive materials adjust a frequency of light absorption property of the release layer. 8. The system of claim 6 , wherein the release layer absorbs a frequency of light radiated from the laser. 9. The system of claim 6 , wherein the handler is one of: a handle wafer; a panel; and a roll of handler material.

Assignees

Inventors

Classifications

  • the bond interface between the auxiliary support and the wafer comprising two or more, e.g. multilayer adhesive or adhesive and release layer · CPC title

  • of die-attach connectors · CPC title

  • of bump connectors · CPC title

  • batch processes · CPC title

  • On different surfaces · CPC title

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What does patent US10325785B2 cover?
Various embodiments process semiconductor devices. In one embodiment, a release layer is applied to a handler. The at least one singulated semiconductor device is bonded to the handler. The at least one singulated semiconductor device is packaged while it is bonded to the handler. The release layer is ablated by irradiating the release layer through the handler with a laser. The at least one si…
Who is the assignee on this patent?
IBM
What technology area does this patent fall under?
Primary CPC classification H10W74/019. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jun 18 2019 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 6 related publications on this page (citations in our corpus or others sharing the same primary CPC).