Silicon nitride substrate and silicon nitride circuit board using the same

Patent metadata

Field	Value
Publication number	US-10322934-B2
Application number	US-201715833113-A
Country	US
Kind code	B2
Filing date	Dec 6, 2017
Priority date	Oct 23, 2013
Publication date	Jun 18, 2019
Grant date	Jun 18, 2019

Abstract

A silicon nitride substrate including silicon nitride crystal grains and a grain boundary phase and having a thermal conductivity of 50 W/m·K or more, wherein, in a sectional structure of the silicon nitride substrate, a ratio (T2/T1) of a total length T2 of the grain boundary phase in a thickness direction with respect to a thickness T1 of the silicon nitride substrate is 0.01 to 0.30, and a variation from a dielectric strength mean value when measured by a four-terminal method in which electrodes are brought into contact with a front and a rear surfaces of the substrate is 20% or less. The dielectric strength mean value of the silicon nitride substrate can be 15 kV/mm or more. According to above structure, there can be obtained a silicon nitride substrate and a silicon nitride circuit board using the substrate in which variation in the dielectric strength is decreased.

First claim

The invention claimed is:

1. A silicon nitride substrate containing at least one element selected from rare earth element, magnesium, titanium and hafnium as a sintering aid in a total amount of 2 to 14 mass % in terms of oxide content, and comprising silicon nitride crystal grains and a grain boundary phase and having a thermal conductivity of 50 W/m·K or more, wherein, in a sectional structure of the silicon nitride substrate, a ratio, T 2 /T 1 , of a total length T 2 of the grain boundary phase in a thickness direction with respect to a thickness T 1 of the silicon nitride substrate is 0.01 to 0.30, an average grain diameter with respect to a long diameter of the silicon nitride crystal grains is between 1.5 and 10 μm, and a variation from a dielectric strength mean value when measured by a four-terminal method in which electrodes are brought into contact with front and rear surfaces of the substrate is 20% or less, and wherein a ratio (ρv2/ρv1) between a volume resistivity value ρv1 when a voltage of 1000 V is applied at room temperature (25° C.) and a volume resistivity value ρv2 when a voltage of 1000 V is applied at 250° C. is 0.20 or more.

2. The silicon nitride substrate according to claim 1 , wherein a variation in the dielectric strength is 15% or less.

3. The silicon nitride substrate according to claim 1 , wherein the dielectric strength mean value is 15 kV/mm or more.

4. The silicon nitride substrate according to claim 1 , wherein a volume resistivity value when a voltage of 1000 V is applied at 25° C. is 60×10 12 Ωm or more.

5. The silicon nitride substrate according to claim 1 , wherein, when a relative dielectric constant at 50 Hz is represented by ε r50 and a relative dielectric constant at 1 kHz is represented by ε r1000 , (ε r50 −ε r1000 )/ε r50 ≤0.1.

6. The silicon nitride substrate according to claim 1 , wherein, when a cross section in a thickness direction of the silicon nitride substrate is observed with an enlarged photograph, a maximum length of the grain boundary phase is 50 μm or less.

7. The silicon nitride substrate according to claim 1 , wherein a porosity of the silicon nitride substrate is 3% or less.

8. The silicon nitride substrate according to claim 1 , wherein, when an arbitrary surface or cross section of the silicon nitride substrate is observed with an enlarged photograph, a maximum diameter of a pore is 0 μm or more and no more than 20 μm.

9. The silicon nitride substrate according to claim 1 , wherein the substrate has pores, and when an arbitrary cross section of the silicon nitride substrate is observed with an enlarged photograph, a maximum diameter of a pore is greater than 0 μm and no more than 20 μm, and a grain boundary phase component is present at 10% or more of a circumferential length of a pore.

10. The silicon nitride substrate according to claim 1 , wherein, when an arbitrary cross section of the silicon nitride substrate is observed, a maximum length of a segregated region in the grain boundary phase is 0 μm or more and no more than 5 μm.

11. The silicon nitride substrate according to claim 1 , wherein the thickness T 1 of the silicon nitride substrate is from 0.1 to 1.0 mm.

12. The silicon nitride substrate according to claim 1 , wherein, in terms of an area ratio, 20% or more of the grain boundary phase is a crystallized compound phase.

13. A silicon nitride circuit board in which a circuit portion is provided on a silicon nitride substrate according to claim 1 .

14. The silicon nitride substrate according to claim 1 , wherein a maximum diameter of a pore is 3 μm or less.

15. The silicon nitride substrate according to claim 1 , wherein the thickness T 1 of the silicon nitride substrate is from 0.15 to 0.25 mm.

16. The silicon nitride substrate according to claim 1 , wherein the silicon nitride substrate is used as a substrate for a pressure-contact structure.

Assignees

• Toshiba Kk
• Toshiba Materials Co Ltd

Inventors

• Nakayama Noritaka
• Aoki Katsuyuki
• Sano Takashi

Classifications

• H10W70/664

  Carbon-based materials, e.g. fullerenes · CPC title

• H10W70/692

  Ceramics or glasses · CPC title

• H10W70/69

  Insulating materials thereof · CPC title

• H10W70/65

  Shapes or dispositions of interconnections · CPC title

• H10W40/259

  Ceramics or glasses (H10W40/254, H10W40/257, H10W40/255, H10W40/251, H10W40/253 take precedence) · CPC title