Bidirectional current sense amplifier

US10320346B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10320346-B2
Application numberUS-201815877804-A
CountryUS
Kind codeB2
Filing dateJan 23, 2018
Priority dateAug 23, 2017
Publication dateJun 11, 2019
Grant dateJun 11, 2019

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

In a general aspect, a current sense amplifier circuit (CSA) can include a null amplifier path and a main amplifier path that are both configured to receive a differential input voltage. The null amplifier path can output a first differential output voltage based on the differential input voltage. The main amplifier path can also be configured to receive the first differential output voltage and output a second differential output voltage based on the differential input voltage and the first differential output voltage. The null and main amplifier paths can each include a differential amplifier having first and second input stages that are each configured to receive the differential input voltage. The first input stage and the second input stage of the main amplifier path can and be powered by a respective (first and second) floating voltage supply rails that are referenced to a floating ground rail.

First claim

Opening claim text (preview).

What is claimed is: 1. A current sense amplifier circuit comprising: a null amplifier path configured to receive a differential input voltage and to output a first differential output voltage based on the differential input voltage; and a main amplifier path configured to: receive the differential input voltage; receive the first differential output voltage; and output a second differential output voltage based on the differential input voltage and the first differential output voltage, each of the null amplifier path and the main amplifier path including a differential amplifier having a first input stage and a second input stage that are each configured to receive the differential input voltage, the first input stage of the main amplifier path being powered by a first floating voltage supply rail that is referenced to a floating ground rail, the second input stage of the main amplifier path being powered by a second floating voltage supply rail that is referenced to the floating ground rail, the first input stage of the null amplifier path being powered by a third floating voltage supply rail that is referenced to the floating ground rail, and the second input stage of the null amplifier path being powered by a fourth floating voltage supply rail that is referenced to the floating ground rail. 2. The current sense amplifier circuit of claim 1 , wherein the differential amplifier of the main amplifier path includes a third input stage configured to receive the first differential output voltage from the null amplifier path, the third input stage being powered from a constant internal supply voltage of the current sense amplifier circuit that is referenced to an externally supplied ground voltage of the current sense amplifier circuit. 3. The current sense amplifier circuit of claim 1 , wherein at least one of the differential amplifier of the main amplifier path and the differential amplifier of the null amplifier path includes a transconductance compensation circuit coupled between the first input stage and the second input stage, the transconductance compensation circuit being configured to control operation of the second input stage based on operation of the first input stage. 4. The current sense amplifier circuit of claim 3 , wherein the transconductance compensation circuit is configured to, based on operation of the first input stage, produce a current that biases one or more transistors of the differential amplifier to regulate a tail current of the second input stage. 5. The current sense amplifier circuit of claim 1 , wherein: the first floating voltage supply rail and the second floating voltage supply rail are operationally coupled with a first differential input of the current sense amplifier circuit; and the third floating voltage supply rail and the fourth floating voltage supply rail are operationally coupled with a second differential input of the current sense amplifier circuit. 6. The current sense amplifier circuit of claim 1 , further comprising a voltage selection circuit that is configured to: receive a first differential input signal of the differential input voltage; receive a second differential input signal of the differential input voltage; receive an internal supply voltage of the current sense amplifier; select a first voltage having a highest value from the first differential input signal, and the internal supply voltage; apply the selected first voltage to the first floating voltage supply rail; select a second voltage having a highest value from the second differential input signal, and the internal supply voltage; and apply the selected second voltage to the third floating voltage supply rail. 7. The current sense amplifier circuit of claim 6 , wherein the voltage selection circuit is further configured to: apply the first differential input signal to the second floating voltage supply rail; and apply the second differential input signal to the fourth floating voltage supply rail. 8. The current sense amplifier circuit of claim 6 , wherein the voltage selection circuit is an analog voltage selection circuit. 9. The current sense amplifier circuit of claim 6 , wherein the voltage selection circuit includes a voltage regulator configured to determine, from at least one of the selected first voltage and the selected second voltage, a floating ground voltage that is applied to the floating ground rail. 10. The current sense amplifier circuit of claim 6 , further comprising a voltage regulator configured to produce the internal supply voltage from an external supply voltage. 11. The current sense amplifier circuit of claim 10 , further comprising an output amplifier configured to receive the second differential output voltage and provide an amplified output voltage that is proportional to the differential input voltage, the output amplifier being powered by the external supply voltage that is referenced to an externally applied electrical ground voltage of the current sense amplifier. 12. The current sense amplifier circuit of claim 6 , wherein the null amplifier path is a chopper-stabilized amplifier path, the chopper-stabilized amplifier path including: an input chopper coupled with an input side of the differential amplifier of the chopper-stabilized amplifier path, the input chopper being powered by a fifth floating voltage supply rail that is referenced to the floating ground rail; an output chopper coupled with an output side of the differential amplifier of the chopper-stabilized amplifier path, the output chopper being powered by the internal supply voltage that is referenced to an externally supplied ground voltage of the current sense amplifier circuit; and a notch filter coupled with the output chopper, the notch filter being configured to provide the first differential output voltage to the differential amplifier of the main amplifier path. 13. The current sense amplifier circuit of claim 12 , wherein the voltage selection circuit is further configured to apply the first differential input signal to the fifth floating voltage supply rail. 14. A current sense amplifier circuit comprising: a null amplifier path configured to receive a differential input voltage and to output a first differential output voltage based on the differential input voltage; and a main amplifier path configured to: receive the differential input voltage; receive the first differential output voltage; and output a second differential output voltage based on the differential input voltage and the first differential output voltage, each of the null amplifier path and the main amplifier path including a differential amplifier having: a first input stage configured to receive the differential input voltage; a second input stage configured to receive the differential input voltage; and a transconductance compensation circuit coupled between the first input stage and the second input stage, the transconductance compensation circuit being configured to control operation of the second input stage based on operation of the first input stage. 15. The current sense amplifier circuit of claim 14 , wherein the transconductance compensation circuit is configured to, based on operation of the first input stage, produce a current that biases one or more transistors of the differential amplifier to regulate a tail current of the second input stage. 16. The current sense amplifier circuit of claim 14 , wherein the transconductance compensation circuit is configured to turn on the second input stage in response to the first input staging turning off, wherein

Assignees

Inventors

Classifications

  • Complementary long tailed pairs having parallel inputs and being supplied in parallel · CPC title

  • the current being sensed · CPC title

  • by using a signal derived from the output signal, e.g. bootstrapping the voltage supply · CPC title

  • H03F3/393Primary

    with field-effect devices · CPC title

  • the DC-isolation amplifier, e.g. chopper amplifier, modulation/demodulation amplifier, uses capacitive isolation means, e.g. capacitors · CPC title

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Frequently asked questions

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What does patent US10320346B2 cover?
In a general aspect, a current sense amplifier circuit (CSA) can include a null amplifier path and a main amplifier path that are both configured to receive a differential input voltage. The null amplifier path can output a first differential output voltage based on the differential input voltage. The main amplifier path can also be configured to receive the first differential output voltage an…
Who is the assignee on this patent?
Semiconductor Components Ind Llc
What technology area does this patent fall under?
Primary CPC classification H03F3/393. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jun 11 2019 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).