Array substrate and method for making same

Patent metadata

Field	Value
Publication number	US-10319752-B2
Application number	US-201615252900-A
Country	US
Kind code	B2
Filing date	Aug 31, 2016
Priority date	Sep 18, 2015
Publication date	Jun 11, 2019
Grant date	Jun 11, 2019

Abstract

An array substrate includes a substrate, a first insulator layer on the substrate, a second insulator layer on the first insulator layer, a third insulator layer on the second insulator layer, and a first TFT and a second TFT on the substrate. The second TFT includes a second gate electrode on the first insulator layer, a second channel layer on the second insulator layer, and a second source electrode and a second drain electrode on the third insulator layer. The third insulator layer covers the second channel layer and defines a second source hole and a second drain hole.

First claim

What is claimed is:

1. An array substrate comprising:
a substrate;
a first insulator layer formed on the substrate;
a second insulator layer formed on the first insulator layer;
a third insulator layer formed on the second insulator layer;
a first TFT formed on the substrate, the first TFT comprising a first channel layer on the substrate, a first gate electrode on the first insulator layer, a first source electrode, and a first drain electrode, the first source electrode and the first drain electrode on the third insulator layer;
a storage capacitance layer formed on the substrate; and
a second TFT formed on the substrate, the second TFT comprising a second gate electrode on the first insulator layer, a second channel layer on the second insulator layer, and a second source electrode and a second drain electrode, the second source electrode and the second drain electrode on the third insulator layer;
the first insulator layer covering the first channel layer and the storage capacitance layer; the second insulator layer covering the first gate electrode and the second gate electrode;
wherein the first channel layer and the storage capacitance layer are made of a semiconducting material containing polycrystalline silicon; the second channel layer is made of a semiconducting material containing metal oxide; the third insulator layer covers the second channel layer; a second source hole and a second drain hole are defined to extend through the third insulator layer and overlap the second channel layer; a portion of the third insulator layer between the second drain hole and the second source hole defines a protection portion;
wherein a first source hole and a first drain hole are defined to extend through the third insulator layer, the second insulator layer, and the first insulator layer, and overlap the first channel layer;
the first source electrode extends into the first source hole to electrically couple to the first channel layer;
the first drain electrode extends into the first drain hole to electrically couple to the first channel layer;
a storage capacitance hole is defined to extend through the third insulator layer, the second insulator layer, and the first insulator layer, and overlap the storage capacitance layer;
the second source electrode extends into the second source hole to electrically couple to the second channel layer;
the second drain electrode extends into the second drain hole to electrically couple to the second channel layer; and
the second drain electrode also extends into the storage capacitance hole to electrically couple to the storage capacitance layer.

2. The array substrate of claim 1 , wherein:
the first channel layer is at least partially doped with P-type ions and comprises a non-doped portion not doped with P-type ions, two lightly P-type ion doped portions, and two heavily P-type ion doped portions;
the two lightly P-type ion doped portions are located at opposite sides of the non-doped portion;
each heavily P-type ion doped portion is located at a side of one lightly P-type ion doped portion away from the non-doped portion; and
the heavily P-type ion doped portion has a P-type ion concentration greater than that of the lightly P-type ion doped portion.

3. The array substrate of claim 1 , wherein the first channel layer is doped with N-type ions and comprises an ultra-lightly-doped portion, two lightly-doped portions, and two heavily-doped portions; the two lightly-doped portions are located at opposite sides of the ultra-lightly-doped portion; each heavily-doped portion is located at a side of one lightly-doped portion away from the ultra-lightly-doped portion; the heavily-doped portion has a N-type ion concentration greater than that of the lightly-doped portion; and the lightly-doped portion has a N-type ion concentration greater than that of the ultra-lightly-doped portion.

4. The array substrate of claim 1 , wherein the array substrate further comprises a fourth insulator layer formed on the third insulator layer, a fifth insulator layer formed on the fourth insulator layer, a first electrode layer formed on the fourth insulator layer, and a second electrode layer formed on the fifth insulator layer; the first electrode layer is covered by the fifth insulator layer; the fourth insulator layer defines a first connecting hole corresponding to the second drain electrode and passing through the fourth insulator layer; the fifth insulator layer defines a second connecting hole corresponding to the first connecting hole and passing through the fifth insulator layer and the fourth insulator layer; the second electrode layer extends into the second connecting hole to electrically couple to the second drain electrode.

5. The array substrate of claim 1 , wherein the array substrate further comprises a third TFT formed on the substrate, the third TFT comprises a third channel layer on the substrate, a third gate electrode on the first insulator layer, and a third source electrode and a third drain electrode on the third insulator layer and electrically coupled to the third channel layer; the third channel layer is made of a semiconducting material containing polycrystalline silicon doped with P-type ions and comprises a ultra-lightly-doped portion, two lightly-doped portions, and two heavily-doped portions; the two lightly-doped portions are located at opposite sides of the ultra-lightly-doped portion; each heavily-doped portion is located at a side of one lightly-doped portion away from the ultra lightly-doped portion; the heavily-doped portion has a P-type ion concentration greater than that of the lightly-doped portion;
and the lightly-doped portion has a P-type ion concentration greater than that of the ultra-lightly-doped portion.

6. An array substrate comprising:
a substrate, the substrate defining a display area and a peripheral area around the display area;
a first insulator layer, the first insulator layer formed on the substrate and extending from the display area to the peripheral area;
a second insulator layer, the second insulator layer formed on the first insulator layer and extending from the display area to the peripheral area;
a third insulator layer, the third insulator layer formed on the second insulator layer and extending from the display area to the peripheral area;
a first TFT, the first TFT formed on the substrate and positioned in the peripheral area, the first TFT comprising a first channel layer on the substrate, a first gate electrode on the first insulator layer, a first source electrode, and a first drain electrode, the first source electrode and the first drain electrode on the third insulator layer;
a storage capacitance layer formed on the substrate;
a second TFT, the second TFT formed on the substrate and positioned in the display area, the second TFT comprising a second gate electrode on the first insulator layer, a second channel layer on the second insulator layer, a second source electrode, and a second drain electrode, the second source electrode and the second drain electrode on the third insulator layer; and
a third TFT, the third TFT formed on the substrate and positioned in the display area, the third TFT comprising a third gate electrode on the first insulator layer, a third channel layer on the second insulator layer, a third source electrode, and a third drain electrode, the third source electrode and the third drain electrode on the third insulator layer and electrically coupled to the third channel layer;
the first insulator layer covering the first channel layer and the storage capacitance layer; the second insulator layer covering the first gate electrode, the second gate electrode, and the third electrode;
wherein the first channel layer and the storage capacitance layer are made of a semi

Assignees

• Hon Hai Prec Ind Co Ltd

Inventors

• Kao Yi-Chun
• Lin Hsin-Hua

Classifications

• H10P30/204

  into Group IV semiconductors · CPC title

• H10P30/21

  of electrically active species · CPC title

• H01L29/7869

  Electricity · mapped topic

• H01L21/26513

  Electricity · mapped topic

• H01L29/78696

  Electricity · mapped topic