Micro-pillar assisted semiconductor bonding

Patent metadata

Field	Value
Publication number	US-10319693-B2
Application number	US-201514741181-A
Country	US
Kind code	B2
Filing date	Jun 16, 2015
Priority date	Jun 16, 2014
Publication date	Jun 11, 2019
Grant date	Jun 11, 2019

Abstract

Micro pillars are formed in silicon. The micro pillars are used in boding the silicon to hetero-material such as III-V material, ceramics, or metals. In bonding the silicon to the hetero-material, indium is used as a bonding material and attached to the hetero-material. The bonding material is heated and the silicon and the hetero-material are pressed together. As the silicon and the hetero-material are pressed together, the micro pillars puncture the bonding material. In some embodiments, pedestals are used in the silicon as hard stops to align the hetero-material with the silicon.

First claim

What is claimed is:

1. A bonded semiconductor device, the bonded semiconductor device comprising:
a first semiconductor, the first semiconductor comprising:
a substrate; and
a plurality of pillars, wherein:
the plurality of pillars extend from the substrate; and
each pillar of the plurality of pillars comprises:
a proximal end;
a distal end, opposite the proximal end, wherein the proximal end is closer to the substrate than the distal end;
a width equal to or less than 25 microns; and
one or more sides between the proximal end and the distal end;

a second semiconductor, wherein the second semiconductor comprises material not in the first semiconductor; and
a material, wherein:
the material fastens the first semiconductor to the second semiconductor;
the material is a conductor and configured to be an electrical contact between the first semiconductor and the second semiconductor; and
the material surrounds each of the plurality of pillars by contacting the one or more sides of each pillar of the plurality of pillars.

2. The bonded semiconductor device of claim 1 , wherein the plurality of pillars each have a rectangular cross section.

3. The bonded semiconductor device of claim 1 , wherein:
the first semiconductor is made of silicon; and
the plurality of pillars are etched from a same wafer as the substrate.

4. The bonded semiconductor device of claim 3 , wherein the second semiconductor is a composite semiconductor comprising III-V material.

5. The bonded semiconductor device of claim 1 , wherein the substrate further comprises a pedestal, wherein:
a surface of the pedestal is at a first height above a surface of the substrate;
the plurality of pillars extend to a second height above the surface of the substrate; and
the first height is greater than the second height.

6. The bonded semiconductor device of claim 5 , wherein the surface of the pedestal is in contact with the second semiconductor without bonding material being between the surface of the pedestal and the second semiconductor.

7. The bonded semiconductor device of claim 1 , wherein:
a pillar of the plurality of pillars has a first cross section and a second cross section;
the first cross section is parallel to the second cross section;
the first cross section is parallel with the substrate;
the first cross section is closer to the substrate than the second cross section; and
the first cross section has an area larger than the second cross section.

8. A bonded semiconductor device, the bonded semiconductor device comprising:
a first semiconductor, the first semiconductor comprising:
a substrate; and
a plurality of pillars, wherein:
the plurality of pillars extend from the substrate; and
each pillar of the plurality of pillars comprises:
a proximal end;
a distal end, opposite the proximal end, wherein the proximal end is closer to the substrate than the distal end;
a width equal to or less than 25 microns; and
one or more sides between the proximal end and the distal end;

a pillar of the plurality of pillars has a first cross section and a second cross section;
the first cross section is parallel to the second cross section;
the first cross section is closer to the substrate than the second cross section; and
the first cross section has an area less than the second cross section; and

the area of the second cross section is greater than twice the area of the first cross section;

a second semiconductor, wherein the second semiconductor comprises material not in the first semiconductor; and
a material, wherein:
the material fastens the first semiconductor to the second semiconductor; and
the material surrounds each of the plurality of pillars by contacting the one or more sides of each pillar of the plurality of pillars.

9. The bonded semiconductor device of claim 1 , wherein the material comprises indium.

10. The bonded semiconductor device of claim 1 , wherein each pillar of the plurality of pillars comprises silicon and one or more layers of a dielectric and/or metal coating the silicon, such that the one or more layers are between silicon and the material.

11. The bonded semiconductor device of claim 1 , wherein the material has a melting temperature, and the material secures the second semiconductor to the first semiconductor after the material cools below the melting temperature.

12. A semiconductor structure, the semiconductor structure comprising:
a substrate;
a plurality of pillars, wherein:
the plurality of pillars extend from the substrate to a first height; and
each pillar of the plurality of pillars comprises:
a proximal end; and
a distal end, opposite the proximal end, wherein the proximal end is closer to the substrate than the distal end;

a pillar of the plurality of pillars is defined by a first width; and
the first width is equal to or less than 25 microns and the plurality of pillars are configured to puncture an oxide formed on a material, wherein the material is for bonding the semiconductor structure to another semiconductor structure; and

a plurality of pedestals extending from the substrate to a second height, wherein:
the first height is less than the second height;
a pedestal of the plurality of pedestals is defined by a second width; and
the second width is greater than the first width.

13. The semiconductor structure of claim 12 , wherein the second width is equal to or less than 25 μm.

14. The semiconductor structure of claim 12 , wherein the distal end of at least one of the plurality of pillars is pointed by at least:
the at least one of the plurality of pillars having a first cross section and a second cross section;
the first cross section is parallel to the second cross section;
the first cross section is closer to the substrate than the second cross section;
the first cross section is parallel with the substrate; and
the first cross section has an area larger than the second cross section.

15. The semiconductor structure of claim 12 , further comprising:
a second semiconductor, wherein the substrate, the plurality of pillars, and the plurality of pedestals are part of a first semiconductor; and
the material, wherein the material secures the first semiconductor to the second semiconductor, such that:
the material surrounds each of the plurality of pillars, contacting sides of pillars of the plurality of pillars; and
the second semiconductor contacts surfaces of pedestals of the plurality of pedestals.

16. The semiconductor structure of claim 15 , wherein the material has a melting temperature, and the material secures the second semiconductor to the first semiconductor after the material cools below the melting temperature.

17. The semiconductor structure of claim 12 , further comprising the material, wherein the material is configured to form a part of an ohmic contact to the substrate.

18. The semiconductor structure of claim 17 , wherein the material comprises indium.

19. The semiconductor structure of claim 12 , wherein the plurality of pillars are coated with a conducting material used for under-bump metallization.

20. The bonded semiconductor device of claim 5 , further comprising a layer between the pedestal and the second semiconductor, where in the layer prevents direct contact between the pedestal and the second semiconductor.

Assignees

• Skorpios Tech Inc

Inventors

• Lambert Damien

Classifications

• H10P90/1914

  using bonding · CPC title

• H10P10/128

  by direct semiconductor to semiconductor bonding · CPC title

• H10W99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10W90/732

  between stacked chips · CPC title

• H10W90/722

  between stacked chips · CPC title