Fabrication of vertical fuses from vertical fins

Patent metadata

Field	Value
Publication number	US-10319677-B2
Application number	US-201815993042-A
Country	US
Kind code	B2
Filing date	May 30, 2018
Priority date	Feb 6, 2017
Publication date	Jun 11, 2019
Grant date	Jun 11, 2019

Abstract

A vertical fuse element, including, a conductive silicide base on a surface of a substrate, and a conductive silicide pillar extending in a direction perpendicular to the surface of the substrate, where the conductive silicide pillar is on the conductive silicide base, and wherein the conductive silicide pillar includes an upper portion having a width, W 5 , a base having a width, W 6 , and a neck region having a width, W 7 , where W 7 <W 5 , and W 7 ≤W 6 .

First claim

What is claimed is:

1. An array of vertical fuse elements, comprising:
a first conductive silicide base segment and a second conductive silicide base segment on a surface of a substrate; and
a plurality of conductive silicide pillars extending in a direction perpendicular to the surface of the substrate, wherein at least one of the plurality of conductive silicide pillars is on the first conductive silicide base segment and at least one of the plurality of conductive silicide pillars is on the second conductive silicide base segment, and wherein each of the plurality of conductive silicide pillars includes an upper portion having a width, W 5 , a base having a width, W 6 , and a neck region having a width, W 7 , where W 7 <W 5 , and W 7 <W 6 .

2. The array of vertical fuse elements of claim 1 , further comprising, a first metal electrode in electrical contact with the first conductive silicide base segment;
a second metal electrode in electrical contact with the second conductive silicide base segment;
a separate pillar metal electrode in electrical contact with each of the conductive silicide pillars on the first conductive silicide base segment; and
a separate pillar metal electrode in electrical contact with each of the conductive silicide pillars on the second conductive silicide base segment.

3. The array of vertical fuse elements of claim 2 , wherein the first metal electrode and second metal electrode are each selected from the group consisting of tungsten (W), cobalt (Co), titanium (Ti), molybdenum (Mo), nickel (Ni), copper (Cu), tantalum (Ta), ruthenium (Ru), zirconium (Zr), aluminum (Al), platinum (Pt), silver (Ag), gold (Au), tantalum nitride (TaN), titanium nitride (TiN), tantalum carbide (TaN), titanium carbide (TiC), titanium aluminum carbide (TiAlC), and suitable combinations thereof.

4. The array of vertical fuse elements of claim 3 , wherein the material of each conductive silicide pillar is titanium silicide (TiSi), nickel silicide (NiSi), cobalt silicide (CoSi), molybdenum silicide (MoSi), platinum silicide (PtSi), tungsten silicide (WSi), tantalum silicide (TaSi), or suitable combinations thereof.

5. The array of vertical fuse elements of claim 4 , wherein each conductive silicide pillar includes an outer silicide shell and a fin core.

6. The array of vertical fuse elements of claim 4 , wherein the at least one conductive silicide pillar on the first conductive silicide base segment is at least four conductive silicide pillars arranged on the first conductive silicide base segment in a row x column array, and the at least one conductive silicide pillar on the second conductive silicide base segment is at least four conductive silicide pillars arranged on the second conductive silicide base segment in a row x column array.

7. The array of vertical fuse elements of claim 6 , wherein the array of conductive silicide pillars on the first conductive silicide base segment is adjacent to a first region of the substrate having a vertical fin field effect transistor device thereon, and the array of conductive silicide pillars on the second conductive silicide base segment is adjacent to a second region of the substrate having a vertical fin field effect transistor device thereon.

8. The array of vertical fuse elements of claim 7 , wherein the vertical fin field effect transistor device on the first region of the substrate is configured to address the array of conductive silicide pillars on the first conductive silicide base segment for programming the array of conductive silicide pillars.

9. The array of vertical fuse elements of claim 7 , wherein the vertical fin field effect transistor device on the second region of the substrate is configured to address the array of conductive silicide pillars on the second conductive silicide base segment for programming the array of conductive silicide pillars.

10. A method of forming an array of vertical fuse elements on a first region of a substrate adjacent to a second region of the substrate having fin field effect transistors, comprising:
forming a plurality of vertical fins on the substrate;
forming a fin cap on each of the plurality of vertical fins, where each of the fin caps covers an upper portion of one of the plurality of vertical fins and leaves a lower portion of the vertical fin exposed;
reducing the width of the lower portion of each of the vertical fins to form a neck region between the upper portion and the lower portion of the vertical fin;
removing the fin cap from each of the plurality of vertical fins;
forming an amalgamation layer on the plurality of vertical fins; and
heat treating the amalgamation layer and plurality of vertical fins to form conductive silicide pillars from the plurality of vertical fins, and a conductive silicide base from a surface region of the substrate.

11. The method of claim 10 , further comprising, removing at least one of the conductive silicide pillars and a section of the conductive silicide base to form a first conductive silicide base segment and a second conductive silicide base segment on the substrate.

12. The method of claim 11 , further comprising, forming a metal electrode to each of one or more conductive silicide pillar(s) on the first conductive silicide base segment.

13. The method of claim 12 , further comprising forming a blocking layer on a first region of the substrate including the conductive silicide pillar(s) on the first conductive silicide base segment and the conductive second silicide base segment, wherein a second region of the substrate adjacent to the blocking layer includes one or more vertical fins; and
fabricating a fin field effect transistor from each of the one or more vertical fins on the second region of the substrate.

14. The method of claim 13 , where the fin field effect transistor(s) on the second region of the substrate form a logic circuit, a memory circuit, or a combination thereof, and at least one conductive silicide pillar is electrically coupled to the logic circuit, the memory circuit, or the combination thereof.

15. A method of forming a vertical fuse element, comprising:
forming a plurality of vertical fins on a substrate;
forming a neck region in each of a first subset of vertical fins on a first region of the substrate, wherein the neck region is between an upper portion and a lower portion of the vertical fin, and wherein a second subset of vertical fins on a second region of the substrate remains without a neck region.

16. The method of claim 15 , wherein the neck region is formed by forming a sacrificial layer on a lower portion of the vertical fins on the first region of the substrate, and removing the sacrificial layer from the lower portion of each vertical fin.

17. The method of claim 15 , further comprising, forming an amalgamation layer on the vertical fins on the first region of the substrate, and heat treating the amalgamation layer to convert each vertical fin on the first region of the substrate to a conductive silicide pillar.

18. The method of claim 17 , wherein the amalgamation layer is selected from the group of metals consisting of titanium (Ti), nickel (Ni), cobalt (Co), molybdenum (Mo), platinum (Pt), tungsten (W), tantalum (Ta), and combinations thereof.

19. The method of claim 17 , wherein each conductive silicide pillar has a resistivity in the range of about 1×10 −7 Ω−m to about 3×10 −6 Ω−m.

20. The method of claim 17 , wherein each conductive silicide pillar includes an outer silicide shell and a fin core.

Assignees

• IBM

Inventors

• Cheng Kangguo
• Demarest James J
• Li Juntao

Classifications

• H10P50/695

  characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask · CPC title

• H10W20/493 Primary

  Fuses, i.e. interconnections changeable from conductive to non-conductive · CPC title

• H01L29/456

  Electricity · mapped topic

• H01L21/823431

  Electricity · mapped topic

• H01L21/32053

  Electricity · mapped topic