Offset-cancellation sensing circuit (OCSC)-based non-volatile (NV) memory circuits

Patent metadata

Field	Value
Publication number	US-10319425-B1
Application number	US-201815939514-A
Country	US
Kind code	B1
Filing date	Mar 29, 2018
Priority date	Mar 29, 2018
Publication date	Jun 11, 2019
Grant date	Jun 11, 2019

Abstract

Offset-cancellation sensing circuit (OCSC)-based Non-volatile (NV) memory circuits are disclosed. An OCSC-based NV memory circuit includes a latch circuit configured to latch a memory state from an input signal. The OCSC-based NV memory circuit also includes a sensing circuit that includes NV memory devices configured to store the latched memory state in the latch circuit for restoring the memory state in the latch circuit when recovering from a reduced power level in an idle mode. To avoid the need to increase transistor size in the sensing circuit to mitigate restoration degradation, the sensing circuit is also configured to cancel an offset voltage of a differential amplifier in the sensing circuit. In other exemplary aspects, the NV memory devices are included in the sensing circuit and coupled to the differential transistors as NMOS transistors in the differential amplifier, eliminating contribution of offset voltage from other differential PMOS transistors not included.

First claim

What is claimed is:

1. A sensing circuit, comprising:
a differential amplifier, comprising:
an output node configured to receive an output voltage;
a complement output node configured to receive a complement output voltage;
a differential transistor comprising a first gate, a first node, and a second node coupled to a ground node;
a complement differential transistor comprising a second gate, a third node, and a fourth node coupled to the ground node;
a pre-charge control circuit coupled between the first gate and the complement output node, the pre-charge control circuit configured to be activated to couple the first gate to the output node;
a complement pre-charge control circuit coupled between the second gate and the output node, the complement pre-charge control circuit configured to be activated to couple the second gate to the complement output node;
a ground control circuit coupled between the ground node and a capacitor node;
a complement ground control circuit coupled between the ground node and a complement capacitor node;
a capacitor circuit coupled between the first gate and the capacitor node; and
a complement capacitor circuit coupled between the second gate and the complement capacitor node;

a non-volatile (NV) memory circuit coupled between the complement output node and a supply node, the NV memory circuit configured to store a memory state;
a complement NV memory circuit coupled between the output node and the supply node, the complement NV memory circuit configured to store a complement memory state complementary to the memory state; and
a differential amplifier control circuit coupled to a supply voltage node configured to receive a supply voltage and the supply node.

2. The sensing circuit of claim 1 , further comprising:
a second pre-charge control circuit coupled between the capacitor node and the output node; and
a second complement pre-charge control circuit coupled between the complement capacitor node and the complement output node.

3. The sensing circuit of claim 2 , wherein:
the second pre-charge control circuit comprises a first pass gate comprising a gate, a first node coupled to the capacitor node, and a second node coupled to the output node; and
the second complement pre-charge control circuit comprises a second pass gate comprising a gate, a first node coupled to the complement capacitor node, and a second node coupled to the complement output node.

4. The sensing circuit of claim 1 , wherein:
the pre-charge control circuit comprises a pass gate comprising a gate, a first node coupled to the output node, and a second node coupled to the differential transistor; and
the complement pre-charge control circuit comprises a pass gate comprising a gate, a first node coupled to the complement output node, and a second node coupled to the complement differential transistor.

5. The sensing circuit of claim 1 , wherein:
the ground control circuit comprises a transistor comprising a gate, a first node coupled to the capacitor node, and a second node coupled to the ground node; and
the complement ground control circuit comprises a transistor comprising a gate, a first node coupled to the complement capacitor node, and a second node coupled to the ground node.

6. The sensing circuit of claim 1 , wherein:
the NV memory circuit comprises a magnetic tunnel junction (MTJ); and
the complement NV memory circuit comprises a complement MTJ.

7. The sensing circuit of claim 1 , wherein:
the differential transistor comprises an N-type metal-oxide semiconductor (MOS) (NMOS) transistor; and
the complement differential transistor comprises an NMOS transistor.

8. The sensing circuit of claim 1 , wherein:
the differential amplifier control circuit is coupled to a first pre-charge input;
the pre-charge control circuit is coupled to the first pre-charge input;
the complement pre-charge control circuit is coupled to the first pre-charge input;
the ground control circuit is coupled to the first pre-charge input; and
the complement ground control circuit is coupled to the first pre-charge input; and
in response to a first pre-charge input signal on the first pre-charge input indicating a first pre-charge operational phase:
the differential amplifier control circuit is configured to couple the supply voltage to the NV memory circuit and the complement NV memory circuit;
the ground control circuit is configured to couple the capacitor node to the ground node;
the complement ground control circuit is configured to couple the complement capacitor node to the ground node;
the pre-charge control circuit is configured to couple the NV memory circuit to the first gate of the differential transistor to pre-charge the first gate of the differential transistor to a first pre-charge voltage based on the supply voltage, and store the first pre-charge voltage in the capacitor circuit; and
the complement pre-charge control circuit is configured to couple the complement NV memory circuit to the second gate of the complement differential transistor to pre-charge the second gate of the complement differential transistor to a first complement pre-charge voltage based on the supply voltage, and store the first complement pre-charge voltage in the complement capacitor circuit.

9. The sensing circuit of claim 8 , wherein:
the pre-charge control circuit is coupled to an offset-cancellation input;
the complement pre-charge control circuit is coupled to the offset-cancellation input;
the ground control circuit is coupled to the offset-cancellation input; and
the complement ground control circuit is coupled to the offset-cancellation input; and
in response to an offset-cancellation input signal on the offset-cancellation input indicating an offset-cancellation operational phase:
the ground control circuit is configured to couple the capacitor node to the ground node;
the complement ground control circuit is configured to couple the complement capacitor node to the ground node;
the pre-charge control circuit is configured to couple the first gate of the differential transistor to the first node of the differential transistor to discharge the capacitor circuit on the first gate of the differential transistor to a threshold voltage of the differential transistor; and
the complement pre-charge control circuit is configured to couple the second gate of the complement differential transistor to the third node of the complement differential transistor to discharge the first complement pre-charge voltage from the complement capacitor circuit on the first gate of the differential transistor to a complement threshold voltage of the complement differential transistor;
the threshold voltage on the first gate of the differential transistor and the complement threshold voltage of the second gate of the complement differential transistor configured to substantially cancel an offset voltage of the differential amplifier control circuit.

10. The sensing circuit of claim 9 , wherein in response to the offset-cancellation input signal indicating the offset-cancellation operational phase, the differential amplifier control circuit is configured to decouple the supply voltage from the NV memory circuit and the complement NV memory circuit.

11. The sensing circuit of claim 9 , wherein:
the ground control circuit is coupled to a second pre-charge input; and
the complement ground control circuit is coupled to the second pre-charge input; and
in response to a second pre-charge input signal on the second pre-charge input indicating a second pre-charge operational phase:
the ground control circuit is configured to couple the capacitor node to the ground node to pre-char

Assignees

• Qualcomm Inc
• Yonsei Univ Univ Industry Foundation
• Qualcomm Tech Incorporated

Inventors

• Jung Seong-Ook
• Song Byungkyu
• Kim Sungryul
• Kim Jung Pill
• Kang Seung Hyuk

Classifications

• G11C11/1673 Primary

  Reading or sensing circuits or methods · CPC title

• G11C11/1659

  Cell access · CPC title

• G11C7/065

  Differential amplifiers of latching type · CPC title

• G11C7/222

  Clock generating, synchronizing or distributing circuits within memory device · CPC title

• G11C7/24

  Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells · CPC title