Sub-resolution assist feature implementation for shot generation

Patent metadata

Field	Value
Publication number	US-10318697-B2
Application number	US-201615289919-A
Country	US
Kind code	B2
Filing date	Oct 10, 2016
Priority date	Mar 14, 2013
Publication date	Jun 11, 2019
Grant date	Jun 11, 2019

Abstract

A design layout for a semiconductor chip includes information on shapes desired to be fabricated. Clusters of photolithographic exposure “shots” are generated and subject to a measure of shot density to approximate a mask shape that generates the desired fabricated shapes when exposed during wafer fabrication. A simulation is run on the clusters of shots to estimate the resulting fabrication shapes that the clusters of shots create. The clusters of shots are modified to align the estimated fabrication shapes more closely with desired fabrication shapes. The process of simulating and modifying the shots is iterative, repeating until the estimated fabrication shapes are within a desired error difference of the planned fabrication shape.

First claim

What is claimed is:

1. A computer-implemented method for development, characterization, refinement and shape analysis of a semiconductor layout design, the method comprising:
determining a desired fabricated shape based on the semiconductor design layout corresponding to a physical chip, wherein the desired fabricated shape corresponds to the semiconductor design layout;
evaluating the semiconductor design layout to determine mask shapes, wherein the mask shapes are determined comprising analyzing the semiconductor design layout to evaluate desired fabricated shapes;
generating, using one or more processors, shots based on the mask shapes, wherein the generating is accomplished by bypassing a polygon as an intermediate representation of the mask shapes;
estimating a resulting fabricated semiconductor layout based on the shots;
modifying the shots based on the mask shapes to make the resulting fabricated semiconductor layout to be closer to the desired fabricated shape; and
storing information on the shots onto computer storage media.

2. The computer-implemented method of claim 1 further comprising establishing a shot density for shots used to generate the mask shapes.

3. The computer-implemented method of claim 2 wherein the mask shapes include an assist feature.

4. The computer-implemented method of claim 3 further comprising determining assist feature shapes to aid in fabrication of the desired fabricated shape.

5. The computer-implemented method of claim 4 wherein the establishing a shot density for shots is further based on the assist feature shapes.

6. The computer-implemented method of claim 5 wherein the assist feature includes a sub-resolution assist feature shape.

7. The computer-implemented method of claim 6 wherein the shots are used to generate the sub-resolution assist feature shape.

8. The computer-implemented method of claim 5 further comprising generating a semiconductor mask with the mask shapes based on the assist feature.

9. The computer-implemented method of claim 8 wherein the generating of the semiconductor mask is based on the shot density for the shots.

10. The computer-implemented method of claim 1 wherein the mask shapes include an assist feature which is determined comprising:
selecting a glyph that approximates the assist feature; and
placing the glyph within the mask shapes.

11. The computer-implemented method of claim 1 wherein the mask shapes include an assist feature which does not appear on a physical chip based on the semiconductor design layout.

12. The computer-implemented method of claim 1 wherein the modifying the shots occurs based on an optical proximity correction calculation.

13. The computer-implemented method of claim 12 wherein the optical proximity correction calculation occurs within a loop along with the estimating the resulting fabricated semiconductor layout and the modifying the shots.

14. The computer-implemented method of claim 1 further comprising obtaining a library of pre-determined shot clusters representing a plurality of assist shapes for the mask shapes.

15. The computer-implemented method of claim 14 further comprising selecting, from the library, an assist shape from the plurality of assist shapes where the assist shape is based on the desired fabricated shape.

16. The computer-implemented method of claim 1 wherein pre-determined shot clusters that comprise one or more mask shapes comprise glyphs.

17. The computer-implemented method of claim 1 further comprising controlling a variably shaped beam based on the shots.

18. The computer-implemented method of claim 1 further comprising determining a required minimum shot configuration for the shots.

19. The computer-implemented method of claim 1 further comprising correcting the shots to eliminate harmful artifacts.

20. The computer-implemented method of claim 19 further comprising modifying patterns for the shots at boundaries between adjacent glyphs.

21. The computer-implemented method of claim 1 further comprising characterizing the shots to generate pre-determined shot clusters.

22. The computer-implemented method of claim 21 further comprising storing the pre-determined shot clusters into a library.

23. The computer-implemented method of claim 22 wherein the generating allows shot configurations to overlap.

24. The computer-implemented method of claim 23 wherein the generating increases degrees of freedom for determining a minimum shot configuration.

25. The computer-implemented method of claim 1 further comprising:
causing a mask set to be generated in accordance with the modified shots.

26. The computer-implemented method of claim 25 further comprising:
causing the semiconductor design to be fabricated using the mask set.

27. A computational layout tool executing on a computer for development, characterization, refinement, and shape analysis of a semiconductor layout design, comprising:
a memory which stores instructions;
one or more processors coupled to the memory wherein the one or more processors are configured to:
determine a desired fabricated shape based on the semiconductor design layout corresponding to a physical chip, wherein the desired fabricated shape corresponds to the semiconductor design layout;
evaluate the semiconductor design layout to determine mask shapes, wherein the mask shapes are determined comprising analyzing the semiconductor design layout to evaluate desired fabricated shapes;
generate shots based on the mask shapes, wherein the generating is accomplished by bypassing a polygon as an intermediate representation of the mask shapes;
estimate a resulting fabricated semiconductor layout based on the shots;
modify the shots based on the mask shapes to make the resulting fabricated semiconductor layout to be closer to the desired fabricated shape; and
store information on the shots onto computer storage media.

28. A computer program product embodied in a non-transitory computer readable medium, which when executed by a processor, causes the processor to perform development, characterization, refinement, and shape analysis of a semiconductor layout design, the computer program product comprising instructions that when executed cause the processor to:
determine a desired fabricated shape based on the semiconductor design layout corresponding to a physical chip, wherein the desired fabricated shape corresponds to the semiconductor design layout;
evaluate the semiconductor design layout to determine mask shapes, wherein the mask shapes are determined comprising analyzing the semiconductor design layout to evaluate desired fabricated shapes;
generate shots based on the mask shapes, wherein the generating is accomplished by bypassing a polygon as an intermediate representation of the mask shapes;
estimate a resulting fabricated semiconductor layout based on the shots;
modify the shots based on the mask shapes to make the resulting fabricated semiconductor layout to be closer to the desired fabricated shape; and
store information on the shots onto computer storage media.

Assignees

• Synopsys Inc

Inventors

• Rieger Michael Lawrence
• Cecil Thomas Christopher
• Painter Benjamin David

Classifications

• G03F1/70

  Adapting basic layout or design of masks to lithographic process requirements, e.g., second iteration correction of mask patterns for imaging · CPC title

• G06F30/398 Primary

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• G06F30/392

  Floor-planning or layout, e.g. partitioning or placement · CPC title

• G03F1/36 Primary

  Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes · CPC title

• G06F17/5081 Primary

  Physics · mapped topic