Power aware hash function for cache memory mapping

Patent metadata

Field	Value
Publication number	US-10318428-B2
Application number	US-201615262619-A
Country	US
Kind code	B2
Filing date	Sep 12, 2016
Priority date	Sep 12, 2016
Publication date	Jun 11, 2019
Grant date	Jun 11, 2019

Abstract

A multi-core processing chip where the last-level cache functionality is implemented by multiple last-level caches (a.k.a. cache slices) that are physically and logically distributed. The hash function used by the processors on the chip is changed according to which of last-level caches are active (e.g., ‘on’) and which are in a lower power consumption mode (e.g., ‘off’.) Thus, a first hash function is used to distribute accesses (i.e., reads and writes of data blocks) to all of the last-level caches when, for example, all of the last-level caches are ‘on.’ A second hash function is used to distribute accesses to the appropriate subset of the last-level caches when, for example, some of the last-level caches are ‘off.’ The chip controls the power consumption by turning on and off cache slices based on power states, and consequently dynamically switches among at least two hash functions.

First claim

What is claimed is:

1. An integrated circuit, comprising:
a plurality of last-level caches that can be placed in at least a first high power consumption mode and a first low power consumption mode;
a plurality of processor cores to access data in the plurality of last-level caches according to a first hashing function that maps processor access addresses to respective ones of the plurality of last-level caches based at least in part on all of the last-level caches being in the first high power consumption mode, the plurality of processor cores to access data in the plurality of last-level caches according to a second hashing function that maps processor access addresses to a subset of the plurality of last-level caches based at least in part on at least one of the last-level caches being in the first low power consumption mode; and,
an interconnect network to receive hashed access addresses from the plurality of processor cores and to couple each of the plurality of processor cores to a respective one of the plurality of last-level caches specified by the hashed access addresses generated by a respective one of the first and second hashing function.

2. The integrated circuit of claim 1 , wherein the plurality of processor cores includes a low power type processor core and a high power type processor core.

3. The integrated circuit of claim 2 , wherein the low power type processor core is associated with a first one of the last-level caches and the high power type processor core is also associated with the first one of the last-level caches.

4. The integrated circuit of claim 2 , wherein the low power type processor core is associated with a first one of the last-level caches and the high power type processor core is associated with a second one of the last-level caches.

5. The integrated circuit of claim 1 , wherein each of the plurality of processor cores is associated with a respective one of the last-level caches.

6. The integrated circuit of claim 4 , wherein based at least in part on the subset of the plurality of last-level caches being in the first low power consumption mode, the respective ones of the plurality of processor cores most tightly coupled to the respective ones of the subset of the plurality of last-level caches are placed in a second low power consumption mode.

7. The integrated circuit of claim 6 , wherein the subset of the plurality of last-level caches corresponds to the ones of the plurality of last-level caches associated with respective ones of the plurality of processor cores that are in the second low power consumption mode.

8. A method of operating a processing system having a plurality of processor cores, comprising:
based at least in part on a first set of last-level caches of a plurality of last-level caches being in a first power-consumption mode, mapping, using a first hashing function, accesses by a first processor core of the plurality of processor cores to the first set of last-level caches; and,
based at least in part on a second set of last-level caches of the plurality of last-level caches being in the first power-consumption mode, mapping, using a second hashing function, accesses by the first processor core to the second set of last-level caches.

9. The method of claim 8 , wherein the first processor core is more tightly coupled to a first one of the plurality of last-level caches than to other last-level caches of the plurality of last-level caches.

10. The method of claim 9 , wherein the first one of the plurality of last-level caches is in both the first set of last-level caches and the second set of last-level caches.

11. The method of claim 8 , wherein the first processor core is more tightly coupled to a first one of the plurality of last-level caches than to other last-level caches of the plurality of last-level caches and a second processor core is more tightly coupled to a second one of the plurality of last-level caches than to other last-level caches of the plurality of last-level caches.

12. The method of claim 11 , wherein the second last-level cache is in the first set of last-level caches and is not in the second set of last-level caches.

13. The method of claim 12 , wherein when the first set of last-level caches of the plurality of last-level caches are in the first power-consumption mode, the second processor core is in a second power-consumption mode, and when the second set of last-level caches of the plurality of last-level caches are in the first power-consumption mode, the second processor core is in a third power-consumption mode.

14. The method of claim 13 , wherein the first processor core is a low power type processor core and the second processor core is a high-performance type processor core.

15. A method of operating a plurality of processor cores on an integrated circuit, comprising:
distributing accesses by a first processor core to a first set of last-level caches of a plurality of last-level caches using a first hashing function, the first processor core associated with a first last-level cache of the plurality of last-level caches;
distributing accesses by a second processor core to the first set of last-level caches using the first hashing function, the second processor core associated with a second last-level cache of the plurality of last-level caches;
placing the second last-level cache in a first power-consumption mode; and,
while the second last-level cache is in the first power-consumption mode, distributing accesses by the first processor core to a second set of last-level caches using a second hashing function that does not map accesses to the second last-level cache.

16. The method of claim 15 , wherein the first processor core is a low-performance low power consumption type processor core and the second processor core is a high-performance high power-consumption type processor core.

17. The method of claim 15 , further comprising:
distributing accesses by a third processor core to the first set of last-level caches using the first hashing function, the third processor core associated with a third last-level cache of the plurality of last-level caches;
placing the third last-level cache in the first power-consumption mode; and,
while the third last-level cache is in the first power-consumption mode, distributing accesses by the first processor core to a third set of last-level caches using a third hashing function that does not map accesses to either of the second last-level cache and the third last-level cache.

18. The method of claim 17 , wherein the first processor core is a low-performance low power consumption type processor core, the second processor core is the low-performance low power-consumption type processor core, and the third processor core is a high-performance high power consumption type core.

19. The method of claim 15 , wherein based at least in part on the second last-level cache being in the first power-consumption mode, the second processor core is placed in a second power consumption mode.

20. The method of claim 19 , wherein based at least in part on the second processing core being in the second power consumption mode, the second processor core does not perform accesses to memory locations that can be stored in the plurality of last-level caches.

Assignees

• Microsoft Technology Licensing Llc

Inventors

• Lai Patrick P
• Shearer Robert Allen

Classifications

• G06F12/0864 Primary

  using pseudo-associative means, e.g. set-associative or hashing · CPC title

• G06F12/0842

  for multiprocessing or multitasking · CPC title

• Y02D10/13

  Cross-Sectional Technologies · mapped topic

• G06F2212/1028

  Power efficiency · CPC title

• G06F12/0813

  with a network or matrix configuration · CPC title