Reduced power mode of a cache unit

Patent metadata

Field	Value
Publication number	US-9360924-B2
Application number	US-201313904055-A
Country	US
Kind code	B2
Filing date	May 29, 2013
Priority date	May 29, 2013
Publication date	Jun 7, 2016
Grant date	Jun 7, 2016

Abstract

In an embodiment, a processor includes a plurality of cores and a cache unit reserved for a first core of the plurality of cores. The cache unit may include a first cache slice, a second cache slice, and power logic to switch operation of the cache unit between a first operating mode and a second operating mode. The first operating mode may include use of both the first cache slice and the second cache slice. The second operating mode may include use of the first cache slice and disabling the second cache slice. Other embodiments are described and claimed.

First claim

What is claimed is:

1. A processor comprising:
a plurality of cores; and
a cache unit reserved for a first core of the plurality of cores, the cache unit comprising a first cache slice, a second cache slice, and power logic to switch operation of the cache unit between a first operating mode and a second operating mode,
wherein each cache slice comprises a queue, a cache memory, and an interface unit,
wherein the first operating mode comprises use of both the first cache slice and the second cache slice, and
wherein the second operating mode comprises use of the first cache slice disabling the second cache slice, and disabling the cache memory of the first cache slice.

2. The processor of claim 1 , wherein the second operating mode further comprises:
not disabling the queue and the interface unit of the first cache slice.

3. The processor of claim 1 , wherein, in the second operating mode, the first cache slice returns a cache miss.

4. The processor of claim 1 , wherein the processor further comprises a power control unit to generate a request to switch the operation of the cache unit.

5. The processor of claim 4 , wherein the power control unit is to generate the request based on a type of processing task expected to be performed by the first core.

6. The processor of claim 4 , wherein the power logic is to, in response to the request, set at least one configuration register to indicate that the cache unit is to switch to a different operating mode.

7. The processor of claim 6 , wherein the request is to switch from the first operating mode to the second operating mode, and wherein the power logic is further to:
set the at least one configuration register to indicate that the cache unit is to switch to the second operating mode, and
upon exiting a sleep state, switch from the first operating mode to the second operating mode.

8. The processor of claim 6 , wherein the request is to switch from the second operating mode to the first operating mode, and wherein the power logic is further to:
set the at least one configuration register to indicate that the cache unit is to switch to the first operating mode, and
upon exiting a sleep state, switch from the second operating mode to the first operating mode.

9. The processor of claim 1 , wherein the power logic is further to, upon switching to the second operating mode, initiate a count in a cache counter.

10. The processor of claim 9 , wherein the power logic is further to, when the cache counter reaches a maximum count, switch from the second operating mode to the first operating mode.

11. A system comprising:
a multicore processor having a plurality of tiles, each tile including a core and a cache unit, wherein the cache unit is private to the tile, each cache unit comprising:
a first cache slice;
a second cache slice, wherein the first cache slice and the second cache slice each comprise a queue, a cache memory, and an interface unit; and
power logic to switch operation of the cache unit between a first operating mode and a second operating mode, wherein the cache unit is to use the first cache slice and the second cache slice in the first operating mode, and wherein the cache unit is to, in the second operating mode:
disable the second cache slice,
use the first cache slice, and
disable the cache memory of the first cache slice; and

a dynamic random access memory (DRAM) coupled to the multicore processor.

12. The system of claim 11 , wherein the second operating mode comprises:
not disabling the queue and the interface unit of the first cache slice.

13. The system of claim 11 , the multicore processor further comprising a power control unit to generate a request to switch the operation of the cache unit between the first operating mode and the second operating mode.

14. The system of claim 13 , wherein the power control unit is to generate the request when a frequency of sleep states expected in a processing task exceeds a threshold level.

15. The system of claim 14 , wherein the processing task is video processing.

16. A method, comprising:
receiving, by power logic included in a cache unit of a processor, a first request to switch the cache unit from a first operating mode to a second operating mode, wherein the cache unit comprises a first cache slice and a second cache slice, wherein the first cache slice and the second cache slice each include a queue, a cache memory, and an interface unit;
in response to the first request, initiating the second operating mode in the cache unit, the second operating mode including use of the first cache slice, disabling the second cache slice, and disabling the cache memory of the first cache slice.

17. The method of claim 16 , wherein initiating the second operating mode comprises:
in response to the request, setting at least one configuration register to indicate receipt of the first request from a power control unit; and
upon waking from a sleep state, initiating the second operating mode in the cache unit based on the at least one configuration register.

18. The method of claim 16 , further comprising, upon initiating the second operating mode in the cache unit:
initiating a cache counter to perform a count; and
upon reaching a maximum count in the cache counter, switching the cache unit to the first operating mode, the first operating mode comprising use of both the first cache slice and the second cache slice.

19. The method of claim 16 , further comprising:
generating the request based on a type of processing task to be performed by a core associated with the cache unit.

20. The method of claim 16 , wherein the second operating mode includes:
not disabling the queue and the interface unit of the first cache slice.

Assignees

• Intel Corp

Inventors

• Gendler Alexander
• Novakovsky Larisa
• Sabba Ariel
• Tokman Niv

Classifications

• G06F2201/885

  Monitoring specific for caches · CPC title

• G06F12/0811

  with multilevel cache hierarchies · CPC title

• G06F1/3275 Primary

  Power saving in memory, e.g. RAM, cache · CPC title

• Y02B60/1228

  Cross-Sectional Technologies · mapped topic

• G06F1/3206

  Monitoring of events, devices or parameters that trigger a change in power modality · CPC title