Coordination of cache and memory reservation

Patent metadata

Field	Value
Publication number	US-10318425-B2
Application number	US-201715647301-A
Country	US
Kind code	B2
Filing date	Jul 12, 2017
Priority date	Jul 12, 2017
Publication date	Jun 11, 2019
Grant date	Jun 11, 2019

Abstract

A method for coordinating cache and memory reservation in a computerized system includes identifying at least one running application, recognizing the at least one application as a latency-critical application, monitoring information associated with a current cache access rate and a required memory bandwidth of the at least one application, allocating a cache partition, a size of the cache partition corresponds to the cache access rate and the required memory bandwidth of the at least one application, defining a threshold value including a number of cache misses per time unit, determining a reduction of cache misses per time unit, in response to the reduction of cache misses per time unit being above the threshold value, retaining the cache partition, assigning a priority of scheduling memory request including a medium priority level, and assigning a memory channel to the at least one application to avoid memory channel contention.

First claim

What is claimed is:

1. A method for coordinating cache and memory reservation in a computerized system comprising a cache memory, a memory and a memory controller, the method comprising:
identifying at least one application in a set of applications running in the computerized system, wherein the set of applications interacts with the memory through the cache memory and a plurality of memory channels;
identifying latency-critical applications within the set of applications;
based on the identified latency-critical applications exceeding a number of available memory channels, associating at least one cache-bound application and at least one bandwidth-bound application with a certain memory channel;
recognizing whether the at least one application is within the identified latency-critical applications;
in response to the at least one application being recognized as a latency-critical application, monitoring information associated with a current cache access rate and a required memory bandwidth of the at least one application;
based on the monitored information, allocating a cache partition, wherein a size of the cache partition corresponds to the cache access rate and the required memory bandwidth of the at least one application;
defining a threshold value comprising a number of cache misses per time unit;
determining a reduction of cache misses per time unit;
in response to the reduction of cache misses per time unit being above the threshold value, retaining the cache partition, wherein the at least one application comprises a cache-bound application;
based on the cache partition being retained, assigning a priority of scheduling memory request comprising a medium priority level;
based on the assigned priority, assigning a memory channel to the at least one application to avoid memory channel contention.

2. The method of claim 1 , further comprising:
in response to the reduction of cache misses per time unit being below the threshold value, removing the cache partition, wherein the at least one application comprises a bandwidth-bound application;
based on the cache partition being removed, assigning a priority of scheduling memory request comprising a high priority level; and
based on the assigned priority, assigning a memory channel to the at least one application to avoid memory channel contention.

3. The method of claim 1 , further comprising:
checking for an available free memory channel; and
assigning the available free memory channel to the at least one application.

4. The method of claim 1 , wherein memory accesses performed by multiple latency-critical applications are split across different memory channels.

5. The method of claim 1 , wherein memory resources are assigned to the set of applications based on memory resource usage of the set of applications by dynamically assigning cache memory partitions, dynamically assigning memory channel partitions and dynamically assigning priorities to requests of applications in the set of applications provided to the memory controller.

6. The method of claim 1 , wherein the set of applications are distributed across different virtual machines of a virtualized computerized system.

7. A computer system for coordinating cache and memory reservation, the computer system comprising:
one or more processors, one or more computer-readable memories, one or more computer-readable tangible storage devices, and program instructions stored on at least one of the one or more storage devices for execution by at least one of the one or more processors via at least one of the one or more memories, wherein the computer system is capable of performing a method comprising:
identifying at least one application in a set of applications running in the computer system, wherein the set of applications interacts with a memory through a cache memory and a plurality of memory channels;
identifying latency-critical applications within the set of applications;
based on the identified latency-critical applications exceeding a number of available memory channels, associating at least one cache-bound application and at least one bandwidth-bound application with a certain memory channel;
recognizing whether the at least one application is within the identified latency-critical applications;
in response to the at least one application being recognized as a latency-critical application, monitoring information associated with a current cache access rate and a required memory bandwidth of the at least one application;
based on the monitored information, allocating a cache partition, wherein a size of the cache partition corresponds to the cache access rate and the required memory bandwidth of the at least one application;
defining a threshold value comprising a number of cache misses per time unit;
determining a reduction of cache misses per time unit;
in response to the reduction of cache misses per time unit being above the threshold value, retaining the cache partition, wherein the at least one application comprises a cache-bound application;
based on the cache partition being retained, assigning a priority of scheduling memory request comprising a medium priority level;
based on the assigned priority, assigning a memory channel to the at least one application to avoid memory channel contention.

8. The computer system of claim 7 , further comprising:
in response to the reduction of cache misses per time unit being below the threshold value, removing the cache partition, wherein the at least one application comprises a bandwidth-bound application;
based on the cache partition being removed, assigning a priority of scheduling memory request comprising a high priority level; and
based on the assigned priority, assigning a memory channel to the at least one application to avoid memory channel contention.

9. The computer system of claim 7 , further comprising:
checking for an available free memory channel; and
assigning the available free memory channel to the at least one application.

10. The computer system of claim 7 , wherein memory accesses performed by multiple latency-critical applications are split across different memory channels.

11. The computer system of claim 7 , wherein memory resources are assigned to the set of applications based on memory resource usage of the set of applications by dynamically assigning cache memory partitions, dynamically assigning memory channel partitions and dynamically assigning priorities to requests of applications in the set of applications provided to a memory controller.

12. The computer system of claim 7 , wherein the set of applications are distributed across different virtual machines of a virtualized computerized system.

13. A computer program product for coordinating cache and memory reservation, the computer program product comprising:
a computer readable non-transitory article of manufacture tangibly embodying computer readable instructions which, when executed, cause a computer to carry out a method comprising:
identifying at least one application in a set of applications, wherein the set of applications interacts with a memory through a cache memory and a plurality of memory channels;
identifying latency-critical applications within the set of application;
based on the identified latency-critical applications exceeding a number of available memory channels, associating at least one cache-bound application and at least one bandwidth-bound application with a certain memory channel;
recognizing whether the at least one application is within the identified latency-critical applications;
in response to the at least one application being recognized as a

Assignees

• IBM

Inventors

• Birke Robert
• Chen Yiyu
• Rameshan Navaneeth
• Schmatz Martin

Classifications

• G06F11/301

  where the computing system is a virtual computing platform, e.g. logically partitioned systems (virtual machines G06F9/45533; logical partitioning of resources G06F9/5077) · CPC title

• G06F12/0897

  with two or more cache hierarchy levels (with multilevel cache hierarchies G06F12/0811) · CPC title

• G06F11/34

  Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation {; Recording or statistical evaluation of user activity, e.g. usability assessment} · CPC title

• G06F2212/1024

  Latency reduction · CPC title

• G06F12/0877

  Cache access modes · CPC title