Integrated circuit and programmable device

Patent metadata

Field	Value
Publication number	US-10318376-B2
Application number	US-201415317230-A
Country	US
Kind code	B2
Filing date	Jun 18, 2014
Priority date	Jun 18, 2014
Publication date	Jun 11, 2019
Grant date	Jun 11, 2019

Abstract

Provided is an integrated circuit or the like capable of rapidly correcting erroneous data write and making contents of the RAMs that are in the multiple modular redundancy coincident in a case where a logic circuit performs the erroneous data write to the RAMs while operating logic circuits and RAMs at a high speed. In order to solve the problem, the integrated circuit including logic circuits and RAMs for which data write and data read are performed by the logic circuits includes a multiple modular redundancy logic circuits, a plurality of RAMs respectively connected to the multiple modular redundancy logic circuits, and a RAM access correction unit which compares access signals from the multiple modular redundancy logic circuit to the RAMs to detect an erroneous data write and corrects an error of the RAM.

First claim

The invention claimed is:

1. An integrated circuit to rapidly correct erroneous write to make contents of RAMs (random access memories) of multiple modular redundancy coincident with each other, the integrated circuit comprising:
multiple modular redundancy logic circuits having at least triple modular redundancy;
RAMs which are provided in the multiple modular redundancy logic circuits and for which data write and data read are performed by the logic circuit; and
a RAM access correction unit that performs an error correction on the RAM which has received an erroneous access signal using write data written in other RAMs when access signals from the logic circuits to the RAMs are compared and the erroneous signal is detected, wherein
in a case where the access signals from the multiple modular redundancy logic circuit to the RAM are compared and non-coincidence of access signals is detected, the RAM access correction unit regards a value with the largest number of coincidence as a normal signal, regards other values as an abnormal signal, specifies a type of an error of the RAM from the access signal regarded as the normal signal and the access signal regarded as the abnormal signal, and corrects the error,
the RAM access correction unit includes an error detection register that maintains the type of the error of erroneous data write, and
the error detection register represents at least four types of no error, non-execution of write, unauthorized write, and erroneous address.

2. The integrated circuit according to claim 1 ,
wherein the logic circuits perform access to the RAM according to a predetermined clock, and
in a case where an access signal is detected at a certain clock, the RAM access correction unit performs error correction processing of the RAM at the next clock.

3. The integrated circuit according to claim 1 ,
wherein the RAM access correction unit includes a normal address register maintaining an address value of an access signal with the largest number of coincidence and a normal write data register which sets a value of write data of the access signal with the largest number of coincidence in a case where the erroneous data write is detected.

4. The integrated circuit according to claim 1 ,
wherein in a case where the access signals from the multiple modular redundancy logic circuit to the RAM are compared and non-coincidence of access signals is detected, when a command of the access signal regarded as normal is write and a command of the access signal regarded as abnormal is not write, the RAM access correction unit performs write access to a RAM to which an access regarded as abnormal is executed using the address and write data of the access signal regarded as normal, thereby correcting an error.

5. The integrated circuit according to claim 1 ,
wherein in a case where the access signals from the multiple modular redundancy logic circuit to the RAM are compared and non-coincidence of access signals is detected, when a command of the access signal regarded as normal and a command of the access signal regarded as abnormal coincide with each other in terms of write, the addresses coincide with each other, and write data do not coincide with each other, the RAM access correction unit performs write access to a RAM to which an RAM access regarded as abnormal is executed using the address and write data of a RAM access signal regarded as normal, thereby correcting an error.

6. The integrated circuit according to claim 1 ,
wherein in a case where the access signals from the multiple modular redundancy logic circuit to the RAM are compared and non-coincidence of access signals is detected, when a command of the access signal regarded as normal is not write and a command of the access signal regarded as abnormal is write, the RAM access correction unit reads data from the RAMs connected to the multiple modular redundancy logic circuits using the address of the access signal regarded as abnormal and performs write access to the RAM to which the RAM access regarded as abnormal is executed using the data with the largest number of coincidence as normal data, thereby correcting an error.

7. The integrated circuit according to claim 1 ,
wherein in a case where the access signals from the multiple modular redundancy logic circuits to the RAMs are compared and non-coincidence of access signals is detected, when a command of the access signal regarded as normal and a command of the access signal regarded as abnormal coincide with each other in terms of write and the addresses of the access signals do not coincide with each other, the RAM access correction unit performs write access to a RAM to which an RAM access regarded as abnormal is executed using the address and the write data of a RAM access signal regarded as normal, reads data from the RAMs connected to the multiple modular redundancy logic circuits using the address of the access signal regarded as abnormal, and performs write access to the RAM to which the RAM access regarded as abnormal is executed using the data with the largest number of coincidence as normal data, thereby correcting an error.

8. The integrated circuit according to claim 1 ,
wherein the RAM access correction unit includes a buffer of three stages or more which temporarily stores the access signals from the multiple modular redundancy logics circuit to the RAMs, temporarily stores an access signal during correction of the error of the RAM to which a RAM access regarded as abnormal is executed, and performs a comparison after correction of the error of the RAM to which the RAM access regarded as abnormal is executed is ended.

9. The integrated circuit according to claim 1 ,
wherein in a case where the RAM access correction unit detects erroneous data write, an RAM access of a logic circuit generating an error is invalidated until error correction of the erroneous data write is ended.

10. An integrated circuit to rapidly correct erroneous write to make contents of RAMs (random access memories) of multiple modular redundancy coincident with each other, the integrated circuit comprising:
multiple modular redundancy logic circuits having at least triple modular redundancy;
RAMs which are provided in the multiple modular redundancy logic circuits and for which data write and data read are performed by the logic circuit; and
a RAM access correction unit that performs an error correction on the RAM which has received an erroneous access signal using write data written in other RAMs when access signals from the logic circuits to the RAMs are compared and the erroneous signal is detected,
wherein the RAM access correction unit includes an abnormal address register which sets an address value of an access signal other than the access signal with the largest number of coincidence and a normal read data register which reads data from the address set in the abnormal address register of the RAMs connected to the multiple modular redundancy logic circuits and regards a value with the largest number of coincidence as normal data in a case where the erroneous data write is detected.

11. A programmable device that loads logic circuit information maintained in a computer-readable storage medium onto an internal configuration RAM when power is supplied, configures a logic circuit, and is operated to rapidly correct erroneous write to make contents of RAMs (random access memories) of multiple modular redundancy coincident with each other, the programmable device comprising:
a dynamic partial reconfiguring unit which reloads a portion of a logic circuit from the computer-readable storage medium during operation;
multiple modular redundancy logic circuits having at least tri

Assignees

• Hitachi Ltd

Inventors

• Yamada Hiromichi
• Yamada Tsutomu

Classifications

• G11C11/409

  Read-write [R-W] circuits · CPC title

• G11C29/702

  by replacing auxiliary circuits, e.g. spare voltage generators, decoders or sense amplifiers, to be used instead of defective ones · CPC title

• G11C2029/0409

  Online test · CPC title

• G06F11/1068 Primary

  in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence) · CPC title

• G11C11/4076

  Timing circuits (for regeneration management G11C11/406) · CPC title