Apparatuses and methods for simultaneous in data path compute operations

Patent metadata

Field	Value
Publication number	US-10318168-B2
Application number	US-201715626790-A
Country	US
Kind code	B2
Filing date	Jun 19, 2017
Priority date	Jun 19, 2017
Publication date	Jun 11, 2019
Grant date	Jun 11, 2019

Abstract

The present disclosure includes apparatuses and methods for simultaneous in data path compute operations. An apparatus can include a memory device having an array of memory cells and sensing circuitry selectably coupled to the array. A plurality of shared I/O lines can be configured to move data from the array of memory cells to a first portion of logic stripes and a second portion of logic stripes for in data path compute operations associated with the array. The first portion of logic stripes can perform a first number of operations on a first portion of data moved from the array of memory cells to the first portion of logic stripes while the second portion of logic stripes perform a second number of operations on a second portion of data moved from the array of memory cells to the second portion of logic stripes during a first time period.

First claim

What is claimed is:

1. An apparatus, comprising:
an array of memory cells;
sensing circuitry selectably coupled to the array of memory cells;
a controller associated with the array; and
a plurality of input/output (I/O) lines shared as a data path for in data path compute operations associated with the array, wherein:
the plurality of shared I/O lines are selectably coupled to a plurality of logic stripes in the data path and are configured to move data from the array of memory cells to the plurality of logic stripes;
wherein the plurality of logic stripes include a first portion of logic stripes and a second portion of logic stripes; and
wherein the controller is configured to cause the first portion of logic stripes to perform a first number of operations on a first portion of data moved from the array of memory cells to the first portion of logic stripes while the second portion of logic stripes perform a second number of operations on a second portion of data moved from the array of memory cells to the second portion of logic stripes during a first time period.

2. The apparatus of claim 1 , wherein each of the plurality of logic stripes each include a plurality of compute components.

3. The apparatus of claim 1 , wherein the plurality of logic stripes include a third portion of logic stripes that perform a third number of operations during the first time period on a third portion of data moved from the array of memory cells to the first portion of logic stripes.

4. The apparatus of claim 1 , wherein the first number of operations are the same as the second number of operations.

5. The apparatus of claim 1 , wherein the first number of operations are different than the second number of operations.

6. The apparatus of claim 1 , wherein the first portion of logic stripes perform the first number of operations on a fourth portion of data moved from the array of memory cells to the first portion of logic stripes during a second time period.

7. The apparatus of claim 6 , wherein the second portion of logic stripes perform the second number of operations on a fifth portion of data moved from the array of memory cells to the second portion of logic stripes during the second time period.

8. An apparatus, comprising:
an array of memory cells;
sensing circuitry selectably coupled to the array of memory cells;
a plurality of input/output (I/O) lines shared as a data path for in data path compute operations associated with the array, wherein the plurality of I/O lines selectably couples the sensing circuitry to a plurality of logic stripes in the data path of the I/O lines; and
a controller associated with the array, the controller configured to:
direct movement of data from a first subrow of a first row of the array and data from a first subrow of a second row of the array via the I/O lines to a first logic stripe during a first time period;
direct movement of data from a second subrow of the first row of the array and data from a second subrow of the second row of the array via the I/O lines to a second logic stripe and performance of a first number of operations on the data from the first subrow of the first row of the array and data from the first subrow of the second row using the first logic stripe during a second time period; and
direct performance of a second number of operations on the data from the first subrow of the first row of the array and data from the first subrow of the second row during a second time period, wherein the first time period and the second time period at least partially overlap.

9. The apparatus of claim 8 , wherein a first portion of logic stripes includes the first logic stripe.

10. The apparatus of claim 9 , wherein the controller is further configured to: direct performance of the first number of operations using the first portion of logic stripes.

11. The apparatus of claim 10 , wherein the controller is further configured to:
direct performance of the first number of operations using the first portion of logic stripes by performing each successive operation of the first number of operations on successive logic stripes of the first portion of logic stripes.

12. The apparatus of claim 8 , wherein a second portion of logic stripes includes the second logic stripe.

13. The apparatus of claim 12 , wherein the controller is further configured to: direct performance of the second number of operations using the second portion of logic stripes.

14. The apparatus of claim 13 , wherein the controller is further configured to: direct performance of the second number of operations using the second portion of logic stripes by performing each successive operation of the second number of operations on successive logic stripes of the second portion of logic stripes.

15. The apparatus of claim 13 , wherein the controller is further configured to: direct performance of the second number of operations using the second portion of logic stripes by performing each successive operation of the second number of operations on a logic stripe the second portion of logic stripes that was previously used to perform one of the second number of operations.

16. The apparatus of claim 8 , wherein the controller is further configured to:
direct movement of data from a third subrow of the first row of the array and data from a third subrow of the second row of the array via the shared I/O lines to a third logic stripe and performance of a third number of operations on the data from the third subrow of the first row of the array and data from the third subrow of the second row during a third time period using the third logic stripe, wherein the first time period, the second time period, and the third time period at least partially overlap.

17. An apparatus, comprising:
an array of memory cells;
sensing circuitry selectably coupled to the array of memory cells;
a plurality of input/output (I/O) lines shared as a data path for in data path compute operations associated with the array, wherein the plurality of I/O lines selectably couples the sensing circuitry to a plurality of logic stripes in the data path of the I/O lines; and
a controller associated with the array, the controller configured to:
direct movement of a first portion of data from the array to a first logic stripe of a first portion of logic stripes in the data path via the plurality of I/O lines during a first time period;
direct performance of a first operation on the first portion of data using the first logic stripe of the first portion of logic stripes during a second time period; and
direct performance of a second operation on a result of the first operation using a second logic stripe of the first portion of logic stripes during the second time period.

18. The apparatus of claim 17 , wherein the controller is further configured to:
direct movement of the result of the first operation from the first logic stripe to the second logic stripe of the first portion of logic stripes in response to completion of the first operation.

19. The apparatus of claim 17 , wherein the first logic stripe of the first portion of logic stripes is coupled to the second logic stripe of the first portion of logic stripes and the second logic stripe of the first portion of logic stripes is coupled to a third logic stripe of the first portion of logic stripes.

20. The apparatus of claim 17 , wherein the first logic stripe of the first portion of logic stripes is coupled to a first number of latches and a third logic stripe of the first portion of logic st

Assignees

• Micron Technology Inc

Inventors

• Lea Perry V
• Hush Glen E

Classifications

• G11C11/4076

  Timing circuits (for regeneration management G11C11/406) · CPC title

• G11C11/4094

  Bit-line management or control circuits · CPC title

• G11C7/1006 Primary

  Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor · CPC title

• G11C7/106

  Data output latches · CPC title

• G11C11/4093 Primary

  Input/output [I/O] data interface arrangements, e.g. data buffers · CPC title