Inducing heterogeneous microprocessor behavior using non-uniform cooling

Patent metadata

Field	Value
Publication number	US-10317962-B2
Application number	US-201615238452-A
Country	US
Kind code	B2
Filing date	Aug 16, 2016
Priority date	Aug 16, 2016
Publication date	Jun 11, 2019
Grant date	Jun 11, 2019

Abstract

Techniques for inducing heterogeneous microprocessor behavior using non-uniform cooling are described. According to an embodiment, a device is provided that comprises an IC chip comprising a plurality of cores and a cooling apparatus coupled to the integrated chip that cools the integrated chip in association with electrical operation of the plurality of cores. The cooling apparatus cools a first core of the plurality of cores to a lower temperature than a second core of the plurality of cores. In various embodiments, the cooling apparatus comprises a plurality of channels embedded within the integrated chip and the cooling apparatus cools the integrated chip via flow of liquid coolant through the plurality of channels.

First claim

What is claimed is:

1. A system, comprising:
an integrated circuit chip comprising a plurality of cores; and
a cooling apparatus coupled to the integrated circuit chip that cools the integrated circuit chip in association with electrical operation of the plurality of cores, wherein the cooling apparatus comprises one or more flow impedance structures that control a flow of a liquid coolant through respective channels of a plurality of channels embedded within the integrated circuit chip to cool a first core of the plurality of cores to a lower temperature than a second core of the plurality of cores.

2. The system of claim 1 , wherein the first core performs at a higher operation frequency relative to an operation frequency of the second core during the electrical operation of the plurality of cores based on the first core having the lower temperature than the second core.

3. The system of claim 2 , further comprising:
a thread controller that assigns a computational workload to the first core based on a time constraint for completion of the computational workload and the higher operation frequency of the first core.

4. The system of claim 1 , further comprising:
a thread controller that assigns a computational workload to the first core;
a frequency controller that directs the first core to perform the computational workload at a higher operation frequency relative to a frequency of operation of the second core based on a time constraint for completion of the computational workload; and
a cooling controller that directs the cooling apparatus to cool the first core to the lower temperature than the second core based on the higher operation frequency.

5. The system of claim 1 , wherein the first core performs at a higher operation frequency relative to an operation frequency of the second core during the electrical operation of the plurality of cores, and wherein the first core is selected to perform at the higher operation frequency relative to the operation frequency of the second core based on a micro-architecture of the integrated circuit chip.

6. The system of claim 1 , wherein the cooling apparatus further comprises a heat exchanger connected to the plurality of channels, and wherein the cooling apparatus further cools the integrated circuit chip via removal of heat from the liquid coolant via the heat exchanger after the liquid coolant is expelled from the plurality of channels.

7. The system of claim 1 , wherein the cooling apparatus further comprises a condenser connected to the plurality of channels, and wherein the cooling apparatus further cools the integrated circuit chip via boiling of the liquid coolant within the plurality of channels and condensing vapor resulting from the boiling via the condenser.

8. The system of claim 1 , wherein the one or more flow impedance structures are electrically controllable to change a size or a position of the one or more flow impedance structures to control the flow of the liquid coolant through the respective channels.

9. The system of claim 8 , further comprising:
one or more thermal sensors that detects respective temperatures of respective cores of the plurality of cores during the electrical operation of the plurality of the cores;
a cooling controller that changes the size or the position of the one or more flow impedance structures based on the respective temperatures; and
a thread controller that schedules computational workloads for the respective cores based on the respective temperatures.

10. A computer-implemented method comprising:
cooling, by a device operatively coupled to a multi-core processor, a first core of a plurality of cores of the multi-core processor to a lower temperature than a second core of the plurality of cores, wherein the plurality of cores are provided on one or more integrated circuit chips, and the cooling comprises manipulating one or more flow impedance structures to control a flow of a liquid coolant through respective channels of a cooling apparatus embedded within the one or more integrated circuit chips; and
directing, by the device, the first core to perform a computational workload at a higher frequency of operation relative to a frequency of operation employed by the second core of the plurality of cores based on the cooling.

11. The computer-implemented method of claim 10 , wherein the cooling apparatus comprises a heat exchanger that removes heat from the liquid coolant after the liquid coolant is expelled from the plurality of channels, and wherein the manipulating comprises impeding the flow of the liquid coolant to one or more channels of the plurality of channels adjacent to the second core.

12. The computer-implemented method of claim 10 , wherein the cooling apparatus comprises a condenser that condenses vapor resulting from boiling of the liquid coolant in the plurality of channels, and wherein the manipulating comprises impeding the flow of the liquid coolant to one or more channels of the plurality of channels adjacent to the first core.

13. The computer-implemented method of claim 10 , further comprising:
identifying, by the device, a first subset of cores of the plurality of cores for operating at the higher frequency relative to a second subset of cores of the plurality of cores, wherein the first subset of cores comprises the first core and the second subset of cores comprises the second core; and
configuring, by the device, the cooling apparatus to cool the first subset of cores to lower temperatures than the second subset of core.

14. The computer-implemented method of claim 10 , wherein the manipulating comprises adjusting a size or a position of the one or more flow impedance structures to control the flow of the liquid coolant through the respective channels.

15. A computer-implemented method comprising:
assigning, by a device operatively coupled to a multi-core processor, a computational workload to a first core of a plurality of cores of the multi-core processor, wherein the plurality of cores are provided on one or more an integrated circuit chips;
directing, by the device based on the computational workload, the first core to perform the computational workload at a higher frequency of operation relative to a frequency of operation employed by a second core of the plurality of cores; and
cooling, by the device, the first core to a lower temperature relative to the second core based on the directing, wherein the cooling comprises manipulating one or more flow impedance structures control a flow of a liquid coolant through respective channels of a cooling apparatus embedded within the one or more integrated circuit chips.

16. The computer-implemented method of claim 15 , wherein the directing comprises directing the first core to perform the computational workload at the higher frequency based on a time constraint for performance of the computational workload.

17. The computer-implemented method of claim 15 , wherein the cooling apparatus comprises a heat exchanger that removes heat from the liquid coolant after the liquid coolant is expelled from the plurality of channels, and wherein the manipulating comprises impeding the flow of the liquid coolant to one or more channels of the plurality of channels adjacent to the second core.

18. The computer-implemented method of claim 15 , wherein the cooling apparatus comprises a condenser that condenses vapor resulting from boiling of the liquid coolant in the plurality of channels, and wherein the manipulating comprises impeding the flow of the liquid coolant to one or more channels of the p

Assignees

• IBM

Inventors

• Bose Pradip
• Buyuktosunoglu Alper
• Chainer Timothy Joseph
• Parida Pritish Ranjan
• Vega Augusto Javier

Classifications

• G06F2200/201

  Cooling arrangements using cooling fluid · CPC title

• G06F1/324

  by lowering clock frequency · CPC title

• G06F1/3206

  Monitoring of events, devices or parameters that trigger a change in power modality · CPC title

• G06F1/206 Primary

  comprising thermal management · CPC title

• Y02D10/126

  Cross-Sectional Technologies · mapped topic