Optimizing core utilization in neurosynaptic systems

Patent metadata

Field	Value
Publication number	US-10317930-B2
Application number	US-201514871680-A
Country	US
Kind code	B2
Filing date	Sep 30, 2015
Priority date	Sep 30, 2015
Publication date	Jun 11, 2019
Grant date	Jun 11, 2019

Abstract

A computer-implemented method is provided for optimizing core utilization in a neurosynaptic network. The computer-implemented method comprises identifying one or more unused portions of a neurosynaptic network. Additionally, the computer-implemented method comprises, for each of the one or more unused portions of the neurosynaptic network, disconnecting the unused portion from the neurosynaptic network.

First claim

What is claimed is:

1. A computer-implemented method, comprising:
identifying one or more unused portions of a neurosynaptic network; and
for each of the one or more unused portions of the neurosynaptic network, disconnecting the unused portion from the neurosynaptic network.

2. The computer-implemented method of claim 1 , wherein each of the one or more unused portions comprises one of an unused neuron and an unused axon.

3. The computer-implemented method of claim 2 , wherein an unused neuron comprises a neuron that cannot affect an output of the neurosynaptic network, and an unused axon comprises an axon that cannot affect the output of the neurosynaptic network.

4. The computer-implemented method of claim 2 , wherein identifying the one or more unused portions of the neurosynaptic network includes:
scanning the neurosynaptic network to identify the unused neurons and the unused axons; and
adding the identified unused neurons and the identified unused axons to a queue.

5. The computer-implemented method of claim 4 , wherein, for each unused portion in the queue, disconnecting the unused portion from the neurosynaptic network includes disconnecting the unused portion from at least one of a source, a destination, a connection, and a crossbar.

6. The computer-implemented method of claim 2 , further comprising, after disconnecting each of the one or more unused portions from the neuro synaptic network:
identifying one or more additional unused portions of the neurosynaptic network; and
for each of the one or more additional unused portions of the neurosynaptic network, disconnecting the additional unused portion from the neurosynaptic network.

7. A computer-implemented method, comprising:
identifying independent blocks of a first plurality of cores of a neurosynaptic network; and
reconfiguring the independent blocks onto the first plurality of cores by calculating a new mapping for at least one of the independent blocks, and moving the at least one of the independent blocks to a new location on a different core of the first plurality of cores of the neurosynaptic network in accordance with the new mapping.

8. The computer-implemented method of claim 7 , further comprising updating block-to-block connectivity for each of the at least one of the independent blocks moved to a new location.

9. The computer-implemented method of claim 7 , wherein the neurosynaptic network further comprises a second plurality of cores, wherein all cores of the first plurality of cores have a same first property, and all cores of the second plurality of cores have a same second property, wherein the first property is different than the second property.

10. The computer-implemented method of claim 9 , wherein the first property includes a first time scale, and the second property includes a second time scale.

11. The computer-implemented method of claim 7 , wherein identifying the independent blocks of the first plurality of cores includes identifying only moveable independent blocks of the first plurality of cores, such that unmoveable independent blocks of the first plurality of cores are not reconfigured.

12. The computer-implemented method of claim 7 , wherein the first plurality of cores includes cores of different sizes.

13. The computer-implemented method of claim 12 , wherein a cost function is utilized for reconfiguring the independent blocks onto the first plurality of cores.

14. The computer-implemented method of claim 13 , wherein the cost function is minimized.

15. The computer-implemented method of claim 7 , wherein the new location of the at least one of the independent blocks maximizes a connectivity of the at least one of the independent blocks between the at least one of the independent blocks and another independent block of the different core.

16. The computer-implemented method of claim 7 , wherein identifying the independent blocks of the first plurality of cores includes, for each of the independent blocks:
identifying a number of neurons in the independent block; and
identifying a number of axons in the independent block.

17. The computer-implemented method of claim 16 , wherein reconfiguring the independent blocks onto the first plurality of cores includes sorting the independent blocks into two lists;
wherein a first list of the two lists includes the independent blocks of the first plurality of cores in decreasing order of the number of axons in each independent block; and
wherein a second list of the two lists includes the independent blocks of the first plurality of cores in decreasing order of the number of neurons in each independent block.

18. The computer-implemented method of claim 17 , wherein reconfiguring the independent blocks onto the first plurality of cores includes, for each of the cores:
identifying an independent block at a top of the first list;
identifying an independent block at a top of the second list; and
selecting, from the independent block at the top of the first list and the independent block at the top of the second list, an independent block having a largest larger value, and mapping the selected independent block to the core.

19. A computer program product for optimizing core utilization in a neurosynaptic network, the computer program product comprising a computer readable storage medium having program instructions embodied therewith, wherein the computer readable storage medium is not a transitory signal per se, the program instructions executable by a processor to cause the processor to:
identify, by the processor, one or more unused portions of a plurality of cores of a neurosynaptic network;
for each of the one or more unused portions of the plurality of cores of the neurosynaptic network, disconnect, by the processor, the unused portion from the neurosynaptic network;
identify, by the processor, independent blocks of the plurality of cores of the neurosynaptic network; and
reconfigure, by the processor, the independent blocks onto the plurality of cores by calculating a new mapping for at least one of the independent blocks, and moving the at least one of the independent blocks to a new location on a different core of the neurosynaptic network in accordance with the new mapping.

20. The computer program product of claim 19 , wherein each of the one or more unused portions comprises one of an unused neuron and an unused axon.

Assignees

• IBM

Inventors

• Amir Arnon
• Datta Pallab
• Megiddo Nimrod
• Modha Dharmendra S

Classifications

• G06E1/00 Primary

  Devices for processing exclusively digital data · CPC title

• G06N3/049 Primary

  Temporal neural networks, e.g. delay elements, oscillating neurons or pulsed inputs · CPC title

• G06N3/063

  using electronic means · CPC title

• G06E3/00

  Devices not provided for in group G06E1/00, e.g. for processing analogue or hybrid data · CPC title