Ultra-responsive phase shifters for depletion mode silcon modulators

Patent metadata

Field	Value
Publication number	US-10317710-B2
Application number	US-201816111992-A
Country	US
Kind code	B2
Filing date	Aug 24, 2018
Priority date	May 14, 2013
Publication date	Jun 11, 2019
Grant date	Jun 11, 2019

Abstract

A novel phase shifter design for carrier depletion based silicon modulators, based on an experimentally validated model, is described. It is believed that the heretofore neglected effect of incomplete ionization will have a significant impact on ultra-responsive phase shifters. A low VπL product of 0.3 V·cm associated with a low propagation loss of 20 dB/cm is expected to be observed. The phase shifter is based on overlapping implantation steps, where the doses and energies are carefully chosen to utilize counter-doping to produce an S-shaped junction. This junction has a particularly attractive VπL figure of merit, while simultaneously achieving attractively low capacitance and optical loss. This improvement will enable significantly smaller Mach-Zehnder modulators to be constructed that nonetheless would have low drive voltages, with substantial decreases in insertion loss. The described fabrication process is of minimal complexity; in particular, no high-resolution lithographic step is required.

First claim

What is claimed Is:

1. A method of fabricating an optical modulator device, comprising:
providing a wafer with a semiconductor layer thereon;
forming an optical waveguide in the semiconductor layer, the optical waveguide having a width W; and,
implanting N-type and P-type dopants into the optical waveguide in multiple implantation steps with an overlap to produce an N-type region at one side of the optical waveguide, a P-type region at another side of the optical waveguide, and wherein an injection window of n dopants and an injection window of p dopants have an implantation overlap region width D in the waveguide;
controlling an overlapping ratio D/W to produce a p-type region and an n-type region sharing a non-planar junction interface as viewed in a cross section taken perpendicular to a light propagation direction in said optical waveguide; wherein the non-planar junction interface is configured to form at least two p/n junctions disposed with overlapping p-type and n-type regions in a direction normal to the wafer; and
annealing said implanted optical waveguide;
thereby forming within said optical waveguide a non-planar common junction configured to increase a junction area between said n-type region and said p-type region per unit length of said length dimension of said junction, so as to so as to enhance an overlap between an optical mode in said optical waveguide and said junction area when said optical modulator device is operational.

2. The method according to claim 1 , wherein the non-planar P/N junction interface is shaped according to a shape geometry selected from the group consisting of “U”-shaped, “C”-shaped, and “S”-shaped.

3. The method according to claim 1 , wherein the implanting comprises implanting a first type of dopants in the implantation overlap region to provide a first dopant concentration therein and implanting a second type of dopants in the implantation overlap region to provide a second dopant concentration therein, so that the first dopant concentration exceeds the second dopant concentration in top and bottom portions of the optical waveguide in the implantation overlap region, and the second dopant concentration exceeds the first dopant concentration between the top and bottom portions, and wherein the first type of dopants is one of the N-type or the P-type, and the second type of dopants is the other of the N-type or the P-type.

4. The method according to claim 1 , wherein the implanting comprises:
i) masking the N-type region;
ii) implanting P-type dopants into the P-type region and the implantation overlap region;
iii) masking the P-type region; and
iv) implanting N-type dopants into the N-type region and the implantation overlap region.

5. The method according to claim 4 , wherein the implanting in one of ii) or iv) comprises using two different implantation energies so as to implant one of the P-type dopant or the N-type dopant at a top portion of the optical waveguide and at a bottom portion of the optical waveguide, and wherein the other of ii) or iv) comprises using an intermediate energy so as to implant the other of the P-type dopant and the N-type dopant between the top and bottom portions of the optical waveguide in the implantation overlap region.

6. The method according to claim 1 , wherein the N-type region comprises at least 50 nm wide portion of the waveguide adjacent one side of the implantation overlap region, and the P-type region comprises at least 50 nm wide portion of the waveguide adjacent another side of the implantation overlap region.

7. The method according to claim 1 , wherein the implanting step includes doping a first slab waveguide adjacent to the N-type region to form an N-type contact; and
doping a second slab waveguide adjacent to the P-type region to form a P-type contact.

8. The method according to claim 7 , wherein forming the optical waveguide includes forming the optical waveguide by an anisotropic etch of the semiconductor layer.

9. The method according to claim 7 , further comprising depositing a layer of an insulator conformally on top of the optical waveguide prior to the implanting.

10. The method according to claim 1 , wherein the wafer comprises a silicon-on-insulator wafer.

11. The method according to claim 1 , wherein the annealing comprises rapid thermal annealing (RTA).

12. The method according to claim 1 , wherein the implanting includes a counter-doping technique comprising several implant steps so as to create in the implantation overlap region at least two P/N junctions located one after another in a direction normal to the substrate.

13. The method according to claim 1 , wherein the implantation overlap region is at least 60% of the waveguide in width.

14. The method according to claim 1 , wherein the implantation overlap region width D is at least 100 nm less than the width W.

15. The method according to claims 1 , wherein the overlapping ratio D/W is about 0.8.

Assignees

• Elenion Tech Llc

Inventors

• Baehr-Jones Thomas
• Liu Yang

Classifications

• G02F1/2257

  the optical waveguides being made of semiconducting material · CPC title

• G02F1/0353

  involving an electro-optic TE-TM mode conversion · CPC title

• G02F1/025 Primary

  in an optical waveguide structure (G02F1/017, {G02F1/2257} take precedence) · CPC title

• G02F1/015

  based on semiconductor elements having potential barriers, e.g. having a PN or PIN junction (G02F1/03 takes precedence) · CPC title

• G02F1/011

  in optical waveguides, not otherwise provided for in this subclass · CPC title