RF system with an RFIC and antenna system

Patent metadata

Field	Value
Publication number	US-10317512-B2
Application number	US-201514954395-A
Country	US
Kind code	B2
Filing date	Nov 30, 2015
Priority date	Dec 23, 2014
Publication date	Jun 11, 2019
Grant date	Jun 11, 2019

Abstract

In accordance with an embodiment, a packaged radio frequency (RF) circuit includes a radio frequency integrated circuit (RFIC) disposed on a substrate that has plurality of receiver circuits coupled to receive ports at a first edge of the RFIC, and a first transmit circuit coupled to a first transmit port at a second edge of the RFIC. The packaged RF circuit also includes a receive antenna system disposed on the package substrate adjacent to the first edge of the RFIC and a first transmit antenna disposed on the package substrate adjacent to the second edge of the RFIC and electrically coupled to the first transmit port of the RFIC. The receive antenna system includes a plurality of receive antenna elements that are each electrically coupled to a corresponding receive port.

First claim

What is claimed is:

1. A packaged radio frequency (RF) circuit comprising:
a radio frequency integrated circuit (RFIC) disposed on a package substrate, the RFIC comprising a plurality of receiver circuits coupled to receive ports at a first edge of the RFIC, and a first transmit circuit coupled to a first transmit port at a second edge of the RFIC different from the first edge;
a receive antenna system disposed on the package substrate adjacent to the first edge of the RFIC, the receive antenna system comprising a plurality of receive antenna elements that are each electrically coupled to a corresponding receive port;
a first transmit antenna disposed on the package substrate adjacent to the second edge of the RFIC and electrically coupled to the first transmit port of the RFIC;
a first plurality of solder balls disposed on the package substrate adjacent to the RFIC and electrically connected to the RFIC;
a second plurality of solder balls disposed on the package substrate adjacent to the receive antenna system, wherein the second plurality of solder balls are electrically floating; and
a ground wall disposed on the package substrate between the RFIC and the receive antenna system.

2. The packaged RF circuit of claim 1 , wherein:
the RFIC further comprises a second transmit circuit coupled to a second transmit port at a third edge of the RFIC different from the first edge and different from the second edge; and
the RF circuit further comprises a second transmit antenna disposed on the package substrate adjacent to the third edge of the RFIC and electrically coupled to the second transmit port of the RFIC.

3. The packaged RF circuit of claim 2 , wherein the second transmit circuit comprises an input selectable between an unmodulated carrier and a modulated carrier.

4. The packaged RF circuit of claim 3 , wherein the RFIC further comprises a bipolar phase shift key (BPSK) modulator coupled to the second transmit circuit.

5. The packaged RF circuit of claim 2 , wherein the second edge and the third edge are each adjacent to the first edge.

6. The packaged RF circuit of claim 1 , wherein:
each of plurality of receive antenna elements comprises a patch antenna; and
the first transmit antenna comprises a patch antenna.

7. The packaged RF circuit of claim 1 , wherein the receive antenna system includes exactly four receive antenna elements.

8. The packaged RF circuit of claim 1 , wherein the ground wall comprises a plurality of grounded solder balls disposed between the receive antenna system and the RFIC.

9. The packaged RF circuit of claim 1 , wherein the packaged RF circuit is a ball grid array (BGA) package.

10. A system comprising:
a packaged radio frequency (RF) circuit comprising
a radio frequency integrated circuit (RFIC) disposed on a package substrate, the RFIC comprising a plurality of receiver circuits coupled to receive ports at a first edge of the RFIC, a first transmit circuit coupled to a first transmit port at a second edge of the RFIC, and a second transmit circuit coupled to a second transmit port at a third edge of the RFIC, wherein the first edge, the second edge and the third edge are different from each other,
a receive patch antenna system disposed on the package substrate adjacent to the first edge of the RFIC, the receive patch antenna system comprising a plurality of receive patch antenna elements that are each electrically coupled to a corresponding receive port,
a first transmit patch antenna disposed on the package substrate adjacent to the second edge of the RFIC and electrically coupled to the first transmit port of the RFIC,
a second transmit patch antenna disposed on the package substrate adjacent to the third edge of the RFIC and electrically coupled to the second transmit port of the RFIC,
a first plurality of solder balls disposed on the package substrate adjacent to the RFIC and electrically connected to the RFIC,
a second plurality of solder balls disposed on the package substrate adjacent to the receive patch antenna system, wherein the second plurality of solder balls are electrically floating, and
a ground wall disposed on the package substrate between the RFIC and the receive patch antenna system, the ground wall comprising grounded solder balls; and

a circuit board coupled to the packaged radio frequency (RF) circuit via the first plurality of solder balls, the second plurality of solder balls and the grounded solder balls.

11. The system of claim 10 , wherein the circuit board comprises a FR4 layer and a ground plane, wherein the ground plane is disposed on an opposite side of the circuit board from the packaged radio frequency (RF) circuit.

12. The system of claim 10 , wherein the receive patch antenna system includes exactly four receive patch antenna elements.

13. The system of claim 10 , wherein the packaged radio frequency (RF) circuit comprises a ball grid array (BGA) package.

14. A system comprising:
a circuit board;
a radio frequency integrated circuit (RFIC) disposed on the circuit board, the RFIC comprising a plurality of receiver circuits coupled to receive ports at a first edge of the RFIC, a first transmit circuit coupled to a first transmit port at a second edge of the RFIC, and a second transmit circuit coupled to a second transmit port at a third edge of the RFIC, wherein the first edge, the second edge and the third edge are different from each other;
a receive patch antenna system disposed on the circuit board adjacent to the first edge of the RFIC, the receive patch antenna system comprising a plurality of receive patch antenna elements that are each electrically coupled to a corresponding receive port;
a first transmit patch antenna disposed on the circuit board adjacent to the second edge of the RFIC and electrically coupled to the first transmit port of the RFIC;
a second transmit antenna disposed on the circuit board adjacent to the third edge of the RFIC and electrically coupled to the second transmit port of the RFIC;
a first plurality of solder balls disposed on the circuit board adjacent to the RFIC and electrically connected to the RFIC;
a second plurality of solder balls disposed on the circuit board adjacent to the receive patch antenna system, wherein the second plurality of solder balls are electrically floating; and
a ground wall disposed on the circuit board between the RFIC and the receive patch antenna system, the ground wall comprising grounded solder balls.

15. The system of claim 14 , wherein the circuit board comprises a FR4 layer and a ground plane, wherein the ground plane is disposed on an opposite side of the circuit board from the RFIC.

16. The system of claim 14 , wherein the receive patch antenna system includes exactly four receive patch antenna elements.

17. The system of claim 14 , wherein the RFIC comprises a frequency modulated continuous wave (FMCW) radar front-end.

18. The system of claim 17 , further comprising a baseband gesture recognition circuit coupled to the RFIC.

19. The system of claim 18 , wherein the baseband gesture recognition circuit comprises:
a plurality of analog-to-digital converters (ADCs) coupled to intermediate frequency receive outputs of the RFIC; and
an intermediate frequency processor coupled to the plurality of ADCs.

20. The system of claim 14 , wherein the second transmit antenna comprises a patch antenna.

21. The system of claim 14 , wherein the second transmit antenna comprises a Yagi-Uda antenna.

22. A method of operating

Assignees

• Infineon Technologies Ag

Inventors

• Trotta Saverio
• Baheti Ashutosh
• Nasr Ismail
• Huynh Ngoc-Hoa
• Niessner Martin Richard

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W72/241

  Dispositions, e.g. layouts · CPC title

• H10W70/63

  Vias, e.g. via plugs · CPC title

• H10W44/248

  for antennas · CPC title