Dual-column-parallel CCD sensor and inspection systems using a sensor

Patent metadata

Field	Value
Publication number	US-10313622-B2
Application number	US-201615337604-A
Country	US
Kind code	B2
Filing date	Oct 28, 2016
Priority date	Apr 6, 2016
Publication date	Jun 4, 2019
Grant date	Jun 4, 2019

Abstract

A dual-column-parallel image CCD sensor utilizes a dual-column-parallel readout circuit including two pairs of cross-connected transfer gates to alternately transfer pixel data (charges) from a pair of adjacent pixel columns to a shared output circuit at high speed with low noise. Charges transferred along the two adjacent pixel columns at a line clock rate are alternately passed by the transfer gates to a summing gate that is operated at twice the line clock rate to pass the image charges to the shared output circuit. A symmetrical Y-shaped diffusion is utilized in one embodiment to merge the image charges from the two pixel columns. A method of driving the dual-column-parallel CCD sensor with line clock synchronization is also described. A method of inspecting a sample using the dual-column-parallel CCD sensor is also described.

First claim

The invention claimed is:

1. A method of inspecting a sample, the method comprising:
directing and focusing radiation onto the sample;
receiving radiation from the sample and directing received radiation to an image sensor, the sensor comprising a dual-column-parallel CCD including an array of pixels arranged in a plurality of rows and a plurality of associated pairs of adjacent columns, each said associated pair including a first column and a second column;
moving the sample relative to the radiation simultaneously with said receiving;
driving the image sensor with line clock signals that are synchronized to the motion of the sample relative to the radiation, the line clock signals causing first and second charges to be transferred from one said row of the image sensor to an adjacent said row along the first and second columns, respectively, of each associated pair of columns;
driving a row of buffer gates of the image sensor with a buffer clock signal, the buffer clock signal causing said first and second charges to be transferred from an edge row of the first and second columns of each associated pair of columns to first and second buffer gates of the row of buffer gates;
driving with a first transfer clock signal both a first transfer gate in a first row of transfer gates disposed over the first column of each associated pair of columns, and a first fourth transfer gate in a second row of transfer gates disposed over the second column of each associated pair of columns;
driving with a second transfer clock signal both a second transfer gate in the first row of transfer gates disposed over the second column of each associated pair of columns, and a third transfer gate in the second row of transfer gates disposed over the first column of each associated pair of columns;
utilizing a readout circuit including multiple output structures, each said output structure including an analog-to-digital converter (ADC) coupled to a corresponding said associated pair of columns and configured to convert said first and second charges transferred along the first and second columns of said corresponding associated pair of columns to first and second digital numbers, respectively; and
driving the ADC with a clock frequency greater than twice a frequency of the line clock signals;
wherein the first transfer clock signal causes said first charge to be transferred from the first transfer gate to the third transfer gate during a first time period, and
wherein the second transfer clock signal causes said second charge to be transferred from the second transfer gate to the fourth transfer gate during a second time period.

2. The method of claim 1 wherein the first transfer clock signal further causes a third charge to be transferred from the fourth transfer gate in the second row of transfer gates to a summing gate of said corresponding output structure during said first time period, and
wherein the second transfer clock signal further causes said first charge to be transferred from the third transfer gate in the second row of transfer gates to the summing gate of said corresponding output structure during said second time period.

3. The method of claim 1 , further comprising driving a reset gate of each said corresponding output structure with a constant pulse width, the reset gate being connected to a floating diffusion of said each corresponding output structure, which is configured to receive charges from one of the summing gate of said each corresponding output structure and an output gate connected to the summing gate of said each corresponding output structure, wherein driving said reset gate includes utilizing a reset-gate pulse to cause the reset gate to reset said floating diffusion to a reset voltage; and
triggering the ADC to generate a corresponding said digital number at a constant time interval after the reset-gate pulse.

4. The method of claim 1 further comprising driving a fifth transfer gate in a third row of transfer gates of the image sensor with the first transfer clock signal, driving a sixth transfer gate in the third row of transfer gates with the second transfer clock signal, and driving seventh gates in the first, second and third rows of transfer gates with a third transfer clock signal.

5. The method of claim 1 , wherein a frequency of the line clocks varies as the speed of the motion of the sample relative to the radiation varies.

6. The method of claim 5 , further comprising pausing or skipping one cycle of a buffer clock signal to keep the buffer clock signal synchronized with the line clock.

7. The method of claim 5 , further comprising slowing or stretching one cycle of a buffer clock signal to keep the buffer clock signal synchronized with the line clock.

8. An inspection system for inspecting a sample, the inspection system comprising:
a radiation source generating radiation;
optics for directing and focusing radiation onto the sample, receiving radiation reflected or scattered from the sample and directing the received radiation to an image sensor, the image sensor comprising a dual-column-parallel CCD;
a computing system for controlling the inspection system, receiving image data from the image sensor, and analyzing said image data to locate a defect on, or measure a dimension of, the sample;
wherein the dual-column-parallel CCD comprises a rectangular or square array of pixels arranged in a plurality of associated pairs of adjacent pixel columns, each said associated pair including a first pixel column and a second pixel column; and
a readout circuit including multiple output structures, each said output structure configured to receive charges from a corresponding said associated pair of adjacent pixel columns, each said output structure comprising:
a first row of transfer gates coupled to receive first charges from a first pixel of said first pixel column and second charges from a second pixel of said second pixel column, and a second row of transfer gates, the second row of transfer gates configured to receive said first and second charges from the first row of transfer gates;
a summing gate configured to alternately receive said first and second charges from the second row of transfer gates; and
an output circuit configured to alternately receive said first and second charges charge from said summing gate and to alternately transmit said first and second charges to a single floating diffusion and a single output amplifier, whereby said single floating diffusion and said single output amplifier are shared by said first and second pixel columns of said associated pair of adjacent pixel columns,
wherein the first and second rows of transfer gates and said associated pair of adjacent pixel columns are effectively cross-coupled such that a first transfer gate control signal applied to a first transfer gate disposed in the first row and the first pixel column is substantially simultaneously applied to a fourth transfer gate disposed in second row and the second pixel column, and such that a second transfer gate control signal applied to a second transfer gate disposed in the first row and the second pixel column is substantially simultaneously applied to a third transfer gate disposed in the second row and the first pixel column.

9. The inspection system of claim 8 , wherein the optics are further configured to illuminate a line on the sample.

10. The inspection system of claim 8 , wherein the optics are further configured for both normal and oblique illumination of the sample.

11. The inspection system of claim 10 , wherein the sample comprises an unpatterned wafer.

12. The inspection system of claim 10 , wherein each said output structure furth

Assignees

• Kla Tencor Corp

Inventors

• Chuang Yung-Ho Alex
• Zhang Jingjing
• Zamek Sharon
• Fielden John
• Contarato Devis
• Brown David L

Classifications

• G06T7/0008 Primary

  checking presence/absence · CPC title

• H04N25/713 Primary

  Transfer or readout registers; Split readout registers or multiple readout registers · CPC title

• H04N25/71

  Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors · CPC title

• H04N25/72

  using frame transfer [FT] · CPC title

• H04N25/715

  using frame interline transfer [FIT] · CPC title