Baseline wander compensation

Patent metadata

Field	Value
Publication number	US-10312920-B2
Application number	US-201715719973-A
Country	US
Kind code	B2
Filing date	Sep 29, 2017
Priority date	Sep 29, 2017
Publication date	Jun 4, 2019
Grant date	Jun 4, 2019

Abstract

A data recovery circuit provides compensation for baseline wander exhibited by a data signal. An adaptive equalizer generates a recovered data signal from a data input. A level shifter and low-pass filter provide a compensation signal as a function of the recovered data signal. An adaptation engine adjusts the level of the compensation signal to compensate for baseline wander. The adaptive equalizer generates the recovered data signal as a function of the data input and the compensation signal, thereby providing accurate recovery of the data signal.

First claim

What is claimed is:

1. A circuit comprising:
an AC-coupling network configured to receive a data input signal and output a high-pass filtered data signal;
an adaptive equalizer configured to output a recovered data signal;
a level shifter configured to output a level-shifted signal as a function of the recovered data signal;
a low-pass filter configured to output a low-pass filtered signal as a function of the level-shifted signal, the low-pass filtered signal corresponding to a low-frequency component of the data input signal, the adaptive equalizer generating the recovered data signal as a function of the low-pass filtered signal and the high-pass filtered data signal;
an adaptation engine configured to control the level shifter to adjust an amplitude of the level-shifted signal as a function of the recovered data signal; and
a comparator configured to receive a first input, the first input being a combination of the low-pass filtered signal and high-pass filtered data signal, the comparator outputting an error signal to the adaptation engine.

2. The circuit of claim 1 , wherein the comparator is further configured to receive a second input corresponding to the recovered data signal, the comparator outputting the error signal as a function of a difference between the first and second inputs.

3. The circuit of claim 1 , wherein the adaptation engine is further configured to adjust the amplitude of the level-shifted signal as a function of the error signal.

4. The circuit of claim 1 , further comprising a deserializer configured to convert the error signal to a parallel error signal.

5. The circuit of claim 4 , wherein the adaptation engine is further configured to receive the parallel error signal.

6. The circuit of claim 1 , further comprising a combiner configured to combine the high-pass filtered data signal and low-pass filtered signal and output a combined data signal.

7. The circuit of claim 6 , wherein the adaptive equalizer is further configured to output the recovered data signal as a function of the combined data signal.

8. The circuit of claim 1 , wherein the adaptive equalizer includes a decision feedback equalizer (DFE).

9. A circuit comprising:
an AC-coupling network configured to receive a data input signal and output a high-pass filtered data signal;
an adaptive equalizer configured to output a recovered data signal;
a level shifter configured to output a level-shifted signal as a function of the recovered data signal;
a low-pass filter configured to output a low-pass filtered signal as a function of the level-shifted signal, the low-pass filtered signal corresponding to a low-frequency component of the data input signal, the adaptive equalizer generating the recovered data signal as a function of the low-pass filtered signal and the high-pass filtered data signal;
an adaptation engine configured to control the level shifter to adjust an amplitude of the level-shifted signal as a function of the recovered data signal; and
a deserializer configured to convert the recovered data signal to a parallel data signal.

10. The circuit of claim 9 , wherein the adaptation engine is further configured to receive the parallel data signal.

11. A method of recovering a data signal, comprising:
filtering a data input signal at an AC-coupling network to generate a high-pass filtered data signal;
level-shifting a recovered data signal to generate a level-shifted signal;
filtering the level-shifted signal to output a low-pass filtered signal, the low-pass filtered signal corresponding to a low-frequency component of the data input signal;
generating the recovered data signal as a function of the low-pass filtered signal and the high-pass filtered data signal;
adjusting an amplitude of the level-shifted signal as a function of the recovered data signal; and
comparing a first input, the first input being a combination of the low-pass filtered signal and high-pass filtered data signal and outputting an error signal.

12. The method of claim 11 , further comprising receiving a second input corresponding to the recovered data signal and outputting the error signal as a function of a difference between the first and second inputs.

13. The method of claim 11 , further comprising adjusting the amplitude of the level-shifted signal as a function of the error signal.

14. The method of claim 11 , further comprising converting the error signal to a parallel error signal.

15. The method of claim 11 , further comprising combining the high-pass filtered data signal and low-pass filtered signal and outputting a combined data signal.

16. The method of claim 15 , further comprising outputting the recovered data signal as a function of the combined data signal.

17. A method of recovering a data signal, comprising:
filtering a data input signal at an AC-coupling network to generate a high-pass filtered data signal;
level-shifting a recovered data signal to generate a level-shifted signal;
filtering the level-shifted signal to output a low-pass filtered signal, the low-pass filtered signal corresponding to a low-frequency component of the data input signal;
generating the recovered data signal as a function of the low-pass filtered signal and the high-pass filtered data signal;
adjusting an amplitude of the level-shifted signal as a function of the recovered data signal; and
converting the recovered data signal to a parallel data signal.

Assignees

• Cavium Llc

Inventors

• Crain Ethan
• Wang Lu

Classifications

• H03L5/00

  Automatic control of voltage, current, or power · CPC title

• H04L25/03057 Primary

  with a recursive structure (H04L25/03031 takes precedence) · CPC title

• H04L7/048

  using the properties of error detecting or error correcting codes, e.g. parity as synchronisation signal · CPC title

• H04L7/0087

  Preprocessing of received signal for synchronisation, e.g. by code conversion, pulse generation or edge detection · CPC title

• H04L7/0331

  with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock (H04L7/0337 takes precedence) · CPC title