Robust coherent and self-coherent signal processing techniques
US-2015365174-A1 · Dec 17, 2015 · US
US9306775B1 · US · B1
| Field | Value |
|---|---|
| Publication number | US-9306775-B1 |
| Application number | US-201414484209-A |
| Country | US |
| Kind code | B1 |
| Filing date | Sep 11, 2014 |
| Priority date | Sep 11, 2014 |
| Publication date | Apr 5, 2016 |
| Grant date | Apr 5, 2016 |
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
What the patent document calls the invention.
A short plain-language summary of the technical disclosure.
Who owns or filed the patent and who is credited as inventor.
Filing, priority, publication, and grant dates set the timeline.
The legal scope of protection — read this for what is actually claimed.
Technology tags used to group this patent with similar filings.
Prior art links and similar publications in this corpus.
Official abstract text for this publication.
A receiver disposed in a serializer/deserializer (SerDes) system includes a coupling capacitor configured to receive a serial input signal from a transmitter operatively coupled with the receiver via a communication channel established therebetween and to output a capacitance output signal, an equalizer configured to receive a signal including the capacitance output signal having a baseline wander gain subtracted therefrom, a running disparity generator receiving decoded symbols and generating a running disparity signal, and a low-pass filter receiving the running disparity signal and outputting the BLW gain.
Opening claim text (preview).
What is claimed is: 1. A receiver disposed in a serializer/deserializer (Ser Des) system, the receiver comprising: a coupling capacitor configured to receive a serial input signal from a transmitter operatively coupled with the receiver via a communication channel established therebetween and to output a capacitance output signal; an equalizer configured to receive a signal comprising the capacitance output signal having a baseline wander gain subtracted therefrom, and to output an equalized signal; a running disparity generator receiving decoded symbols and generating a running disparity signal; and a low-pass filter receiving the running disparity signal and outputting the baseline wander gain, wherein the coupling capacitor is part of an on-chip alternating current coupling capacitance that causes a high-pass filter to be applied to the received serial input signal and wherein a cut-off frequency of the low-pass filter is equal to that of the high-pass filter at least due to the on-chip alternating current coupling capacitance. 2. The receiver of claim 1 , further comprising a slicer receiving the equalized signal from the equalizer and outputting the decoded symbols. 3. The receiver of claim 2 , wherein the baseline wander gain is generated using the decoded symbols and a direct current (dc) gain of the receiver up to that of the serial input signal. 4. The receiver of claim 2 , wherein the slicer is configured to quantize the equalized signal. 5. The receiver of claim 2 , wherein the slicer is configured to output a transition sample. 6. The receiver of claim 5 , wherein the transition sample comprises sampled values of the capacitance output signal at transitions. 7. The receiver of claim 1 , further comprising an adaptation loop receiving the decoded symbols and outputting a target value for the capacitance output signal. 8. A method for adaptation of baseline wander gain executed by a receiver disposed in a serializer/deserializer (SerDes) system, the method comprising: receiving, by a coupled capacitor, a serial input signal from a transmitter operatively coupled with the receiver via a communication channel established therebetween; outputting, by the coupled capacitor, a capacitance output signal; subtracting a baseline wander gain from the capacitance output signal output by the coupled capacitor prior to inputting the capacitance output signal to an equalizer; generating a running disparity signal with a running disparity generator that is receiving decoded symbols; and applying a low-pass filter to the running disparity signal to obtain the baseline wander gain, wherein the coupled capacitor is part of an on-chip alternating current coupling capacitance that causes a high-pass filter to be applied to the received serial input signal and wherein a cut-off frequency of the low-pass filter is equal to that of the high-pass filter leas due to the on-chip alternating current coupling capacitance. 9. The method of claim 8 , further comprising determining an equalized signal given the capacitance output signal having the baseline wander gain subtracted therefrom. 10. The method of claim 9 , further comprising quantizing the equalized signal. 11. The method of claim 8 , further comprising: determining the baseline wander gain as a function of the running disparity signal. 12. The method of claim 11 , further comprising receiving an equalized signal from the equalizer and outputting the decoded symbols. 13. The method of claim 11 , wherein the baseline wander gain is generated using the decoded symbols and a direct current (dc) gain of the receiver up to that of the serial input signal. 14. The method of claim 8 , further comprising determining a target value for the capacitance output signal using decoded symbols. 15. A computer program product embodied in a non-transitory machine-readable medium having machine-readable program code embodied thereon for performing a method of adaptation of baseline wander gain, the method comprising: receiving a serial input signal; outputting a capacitance output signal using the serial input signal; subtracting a baseline wander gain from the capacitance output signal prior to inputting the capacitance output signal to an equalizer; generating a running disparity signal using decoded symbols; and applying a low-pass filter to the running disparity signal to obtain the baseline wander gain, wherein the coupled capacitor is part of an on-chip alternating current coupling capacitance that causes a high-pass filter to be applied to the received serial input signal and wherein a cut-off frequency of the low-pass filter is equal to that of the high-pass filter at least due to the on-chip alternating current coupling capacitance. 16. The computer program product of claim 15 , further comprising determining an equalized signal given the capacitance output signal having the baseline wander gain subtracted therefrom. 17. The computer program product of claim 15 , further comprising: determining the baseline wander gain as a function of the running disparity signal. 18. The computer program product of claim 17 , further comprising receiving an equalized signal from the equalizer and outputting the decoded symbols. 19. The computer program product of claim 17 , wherein the baseline wander gain is generated using the decoded symbols and a direct current (dc) gain of the receiver up to that of the serial input signal. 20. The computer program product of claim 15 , further comprising determining a target value for the capacitance output signal using decoded symbols.
adaptive, i.e. capable of adjustment during data reception · CPC title
Related publications grouped by family.
Answers are generated from the same data shown on this page.