Resistance change memory device having threshold switching and memory switching characteristics, method of fabricating the same, and resistance change memory device including the same
US-9269901-B2 · Feb 23, 2016 · US
US10312441B1 · US · B1
| Field | Value |
|---|---|
| Publication number | US-10312441-B1 |
| Application number | US-201815948043-A |
| Country | US |
| Kind code | B1 |
| Filing date | Apr 9, 2018 |
| Priority date | Apr 9, 2018 |
| Publication date | Jun 4, 2019 |
| Grant date | Jun 4, 2019 |
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
What the patent document calls the invention.
A short plain-language summary of the technical disclosure.
Who owns or filed the patent and who is credited as inventor.
Filing, priority, publication, and grant dates set the timeline.
The legal scope of protection — read this for what is actually claimed.
Technology tags used to group this patent with similar filings.
Prior art links and similar publications in this corpus.
Official abstract text for this publication.
A tunable resistive element, comprising a first terminal, a second terminal, a dielectric layer and an intercalation layer. The dielectric layer and the intercalation layer are arranged in series between the first terminal and the second terminal. The dielectric layer is configured to form conductive filaments of oxygen vacancies on application of an electric field. The intercalation layer is configured to undergo a topotactic transition comprising an oxygen intercalation in combination with a change in the resistivity of the intercalation layer. A related memory device and a related neuromorphic network comprise resistive memory elements as memory cells and synapses respectively and a corresponding design structure.
Opening claim text (preview).
What is claimed is: 1. A tunable resistive element, comprising a first terminal; a second terminal; a dielectric layer; and an intercalation layer, wherein the dielectric layer and the intercalation layer are arranged in series between the first terminal and the second terminal; the dielectric layer is configured to form conductive filaments of oxygen vacancies; and the intercalation layer is configured to undergo a topotactic transition comprising an oxygen intercalation in combination with a change in the resistivity of the intercalation layer. 2. A tunable resistive element according to claim 1 , wherein the intercalation layer is configured to provide a decreasing resistance with an increasing oxygen level. 3. A tunable resistive element according to claim 1 , wherein the tunable resistive element is configured to provide a first resistance state on application of one or electrical reset-pulses to the resistive element, the first resistance state being characterized by a low oxygen level in the intercalation layer and a fully oxidized dielectric layer; and provide a second resistance state on application of one or more set-pulses, the second resistance state being characterized by a plurality of oxygen paths in the intercalation layer between the dielectric layer and the first or the second terminal; and by conductive filaments of oxygen vacancies in the dielectric layer. 4. A tunable resistive element according to claim 1 , wherein the tunable resistive element is configured to provide one or more intermediate resistance states on application of one or more set-pulses and/or reset pulses, the intermediate resistance states being characterized by conductive filaments of oxygen vacancies in the dielectric layer; and a plurality of oxygen regions extending from the conductive filaments in the intercalation layer towards the first or the second terminal. 5. A tunable resistive element according to claim 1 , wherein the dielectric layer comprises conductive filaments being preformed in a fabrication process. 6. A tunable resistive element according to claim 3 , wherein the intercalation layer is configured such that a difference in free energy levels between the intercalated and not-intercalated layer in the first resistance state and the second resistance state is below 1eV. 7. A tunable resistive element according to claim 1 , wherein the intercalation layer comprises a perovskite or derivatives thereof. 8. A tunable resistive element according to claim 1 , wherein the intercalation layer comprises a material selected from the group consisting of: SrCoO 3-x , SrFrO 3-x , SrMnO 3-x , CaCrO 3-x , BaInO 3-x , SrTiO 3-x , (with 0.5<×<1) and La 2 NiO 4+x , La 2 CuO 4+x with (0<×<0.3). 9. A tunable resistive element as claimed in claim 1 , wherein the dielectric layer comprises a metal-oxide material. 10. A tunable resistive element as claimed in claim 9 , wherein the metal oxide material is selected from the group consisting of: TiO 2 , HfO 2 , CeO 2 and RE 2 O 3 , wherein RE is a rare earth material. 11. A tunable resistive element as claimed in claim 1 , wherein the first terminal and/or the second terminal comprises a metal or metal-oxide. 12. A tunable resistive element as claimed in claim 11 , wherein the metal or metal-oxide is selected from the group consisting of Ti, TiN, TaN, W, WO 3 , RuO 2 and ITO. 13. A tunable resistive element as claimed in claim 1 , wherein the dielectric layer has a thickness between 5 nm and 50 nm. 14. A tunable resistive element as claimed in claim 1 , wherein the intercalation layer has a thickness between 5 nm and 50 nm. 15. A tunable resistive element as claimed in claim 3 , wherein the resistive element is configured to provide a bidirectional resistance curve on application of set-pulses and reset pulses. 16. A memory device comprising a plurality of tunable resistive elements according to claim 1 , the memory device comprising a control unit for applying electrical set pulses and electrical reset pulses as electrical programming pulses to the first terminal and/or the second terminal. 17. A memory device as claimed in claim 16 , wherein the control unit is configured to apply: in a write mode one or more write voltages to the first terminal and the second terminal for writing a resistance state; and in a read mode a read voltage to the first and the second terminal for reading the resistance state. 18. A memory device as claimed in claim 16 , wherein the control unit is configured to: apply one or more electrical set pulses to the resistive elements in order to form the conductive filaments of oxygen vacancies in the dielectric layer and to form conductive oxygen paths between the conductive filaments and the first terminal or the second terminal in the intercalation layer, thereby decreasing the resistance of the resistive element; and apply one or more electrical reset pulses to the resistive elements in order to deform the conductive filaments and to transfer oxygen from the intercalation layer to the dielectric layer, thereby increasing the resistance of the resistive element. 19. A neuromorphic network comprising a plurality of resistive elements according to claim 1 as synapses.
Material having complex metal oxide, e.g. perovskite structure · CPC title
Erasing, e.g. resetting, circuits or methods · CPC title
Write using potential difference applied between cell electrodes · CPC title
Writing or programming circuits or methods · CPC title
Material having simple binary metal oxide structure · CPC title
Related publications grouped by family.
Answers are generated from the same data shown on this page.