Trench gate IGBT

Patent metadata

Field	Value
Publication number	US-10312357-B2
Application number	US-201715798218-A
Country	US
Kind code	B2
Filing date	Oct 30, 2017
Priority date	Dec 22, 2016
Publication date	Jun 4, 2019
Grant date	Jun 4, 2019

Abstract

A high-performance trench gate IGBT is provided. A trench gate IGBT according to one embodiment includes: a semiconductor substrate ( 11 ); a channel layer ( 15 ) provided on the semiconductor substrate ( 11 ); two floating P-type layer ( 12 ) provided on both sides of the channel layer 15 , the floating P-type layers ( 12 ) being deeper than the channel layer ( 15 ); two emitter trenches ( 13 ) disposed between the two floating P-type layers ( 12 ), the emitter trenches ( 13 ) being respectively in contact with the floating P-type layers ( 12 ); at least two gate trenches ( 14 ) disposed between the two emitter trenches ( 13 ); and a source diffusion layer ( 19 ) disposed between the two gate trenches 14 , the source diffusion layer ( 19 ) being in contact with each of the gate trenches ( 14 ).

First claim

What is claimed is:

1. A trench gate insulated gate bipolar transistor (IGBT) comprising:
a substrate;
a first-conductivity-type channel layer provided on the substrate;
two first-conductivity-type floating layers, such that one floating layer is provided on each side of both sides of the channel layer, the first-conductivity-type floating layers being deeper than the channel layer;
two emitter trenches disposed between the two floating layers, the emitter trenches being respectively in contact with the floating layers;
at least two gate trenches disposed between the two emitter trenches;
a source diffusion layer disposed between the two gate trenches, the source diffusion layer being in contact with each of the gate trenches; and
an insulation film on a top surface of the channel layer, the two floating layers, the two emitter trenches, each of the at least two gate trenches, and the source diffusion layer,
wherein the insulation film has a plurality of via holes to provide a contact to the top surface of the channel layer, including a first via hole for contact to the channel layer between each of the at least two gate trenches, a second via hole for contact to the channel layer between a first of the two gate trenches and a first of the two emitter trenches, and a third via hole for contact to the channel layer between a second of the two gate trenches and a second of the two emitter trenches.

2. The trench gate IGBT according to claim 1 , wherein the source diffusion layer is not disposed between the emitter trench and the gate trench.

3. The trench gate IGBT according to claim 1 , further comprising a source diffusion layer disposed between the emitter trench and the gate trench.

4. The trench gate IGBT according to claim 1 , wherein the channel layer disposed between the gate trench and the emitter trench is floating.

5. The trench gate IGBT according to claim 1 , wherein
the contact extends from an upper part of the emitter trench to an upper part of the channel layer between the emitter trench and the gate trench.

6. The trench gate IGBT according to claim 1 , wherein the floating layer is formed to be deeper than the emitter trench.

7. The trench gate IGBT according to claim 1 , further comprising an emitter electrode on a top surface of the insulation film, wherein the contact to the top surface of the channel layer comprises a contact of the emitter electrode to the channel layer.

8. The trench gate IGBT according to claim 1 , wherein, in a plan view, each floating layer is formed in a rectangular shape and an emitter trench respectively associated with each floating layer is formed in a U-shape in contact with three sides of its associated floating layer.

9. A trench gate insulated gate bipolar transistor (IGBT) comprising:
a substrate;
a first-conductivity-type channel layer provided on the substrate;
a first first-conductivity-type floating layer provided on a first side of the channel layer;
a second first-conductivity-type floating layer provided on a second side of the channel layer opposite the first side;
a first emitter trench disposed in the channel layer between the first first-conductivity-type floating layer and the first side of the channel layer, the first emitter trench contacting both the first floating layer and the first side of the channel layer;
a second emitter trench disposed in the channel layer between the second first-conductivity-type floating layer and the second side of the channel layer, the second emitter trench contacting both the second floating layer and second side of the channel layer;
a first gate trench and a second gate trench disposed in the channel layer between the first and second emitter trenches;
a first source diffusion region and a second source diffusion region disposed in the channel layer between the first and second gate trenches, the first source diffusion region being in contact with the first gate trench and the second source diffusion region being in contact with the second gate trench;
an insulation film on a top surface of the channel layer, the first and second floating layers, the first and second emitter trenches, the first and second gate trenches, and the first and second source diffusion regions; and
an emitter electrode on a top surface of the insulation film,
wherein the first and second floating layers are deeper than the channel layer, and
wherein the insulation film has a plurality of via holes to provide a contact of the emitter electrode to the top surface of the channel layer, including a first via hole for contact to the channel layer between each of the two gate trenches, a second via hole for contact to the channel layer between a first gate trench and the first emitter trench, and a third via hole for contact to the channel layer between the second gate trench and the second emitter trench Contact.

10. The trench gate IGBT according to claim 9 , wherein no source diffusion region is disposed between the first emitter trench and the first gate trench or between the second emitter trench and the second gate trench.

11. The trench gate IGBT according to claim 9 , wherein third source diffusion region is disposed between the first emitter trench and the first gate trench and a fourth source diffusion region is disposed between the second emitter trench and the second gate trench.

12. The trench gate IGBT according to claim 9 , wherein the channel layer disposed between the gate trench and the emitter trench is floating.

13. The trench gate IGBT according to claim 9 , wherein, for each of the first and second emitter trenches, the emitter electrode contacts both a portion of the upper surface of the emitter trench and a portion of the upper surface of the channel layer between the emitter trench and an associated gate trench.

14. The trench gate IGBT according to claim 9 , wherein the first and second floating layers are formed to be deeper than the first and second emitter trenches.

15. The trench gate IGBT according to claim 9 , wherein, in a plan view, each of the first and second floating layers is formed in a rectangular shape and each of the first and second emitter trenches, respectively associated with the first and second floating layer, is formed in a U-shape in contact with three sides of its associated floating layer.

Assignees

• Renesas Electronics Corp

Inventors

• Kanda Ryo
• Matsuura Hitoshi
• Kikuchi Shuichi

Classifications

• H01L29/407

  Electricity · mapped topic

• H01L29/4238

  Electricity · mapped topic

• H01L29/0619

  Electricity · mapped topic

• H01L29/0692

  Electricity · mapped topic

• H01L29/7397 Primary

  Electricity · mapped topic