Vertical transport transistors with equal gate stack thicknesses

Patent metadata

Field	Value
Publication number	US-10312237-B2
Application number	US-201816058173-A
Country	US
Kind code	B2
Filing date	Aug 8, 2018
Priority date	May 1, 2017
Publication date	Jun 4, 2019
Grant date	Jun 4, 2019

Abstract

Integrated chips include a first semiconductor device and a second semiconductor device. The first semiconductor device includes a semiconductor channel, a first-type work function layer formed from a first material on the semiconductor channel, and a second-type work function layer formed from a second material on the first-type work function later layer. The second semiconductor device includes a semiconductor channel, a second-type work function layer formed the second material on the semiconductor channel, and a thickness matching layer formed on the second-type work function layer of the second semiconductor device, the thickness matching layer having a thickness roughly equal to a thickness of the first-type work function layer.

First claim

What is claimed is:

1. An integrated chip, comprising:
a first semiconductor device, the first semiconductor device comprising:
a semiconductor channel;
a first-type work function layer formed from a first material on the semiconductor channel; and
a second-type work function layer formed from a second material on the first-type work function later layer; and

a second semiconductor device, the second semiconductor device comprising:
a semiconductor channel;
a second-type work function layer formed from the second material on the semiconductor channel; and
a thickness matching layer formed on the second-type work function layer of the second semiconductor device, the thickness matching layer having a thickness roughly equal to a thickness of the first-type work function layer.

2. The integrated chip of claim 1 , further comprising an inter-device connection that connects the first semiconductor device and the second semiconductor device and comprises portions of the first-type work function layer, the second-type work function layer, and the thickness matching layer.

3. The integrated chip of claim 1 , wherein the first semiconductor device is an n-type transistor and wherein the second semiconductor device is a p-type transistor.

4. The integrated chip of claim 3 , wherein the first-type work function layer comprises an n-type titanium nitride layer, a titanium aluminum carbon layer, and a second titanium nitride layer and wherein the second-type work function layer comprises a p-type titanium nitride layer.

5. The integrated chip of claim 3 , wherein the first semiconductor device further comprises a scavenging layer on the second-type work function layer and wherein the second semiconductor device further comprises a scavenging layer between the second-type work function layer and the thickness matching layer.

6. The integrated chip of claim 5 , wherein the thickness matching layer comprises a material selected from the group consisting of titanium nitride, cobalt, and tungsten.

7. The integrated chip of claim 1 , wherein the first semiconductor device is a p-type transistor and wherein the second semiconductor device is an n-type transistor.

8. The integrated chip of claim 7 , wherein the first-type work function layer comprises a p-type titanium nitride layer and wherein the second-type work function layer comprises an n-type titanium nitride layer and a titanium aluminum carbon layer.

9. The integrated chip of claim 7 , wherein the thickness matching layer comprises a material selected from the group consisting of titanium nitride, cobalt, and tungsten.

10. The integrated chip of claim 7 , wherein the second-type work function layer further comprises a second titanium nitride layer.

11. The integrated chip of claim 1 , wherein the first semiconductor device further comprises a scavenging layer on the second-type work function layer and wherein the second semiconductor device further comprises a scavenging layer between the second-type work function layer and the thickness matching layer.

12. An integrated chip, comprising:
a first semiconductor device, the first semiconductor device comprising:
a semiconductor channel;
a first-type work function layer formed on the semiconductor channel; and
a second-type work function layer formed on the first-type work function layer;

a second semiconductor device, the second semiconductor device comprising:
a semiconductor channel;
a second-type work function layer formed on the semiconductor channel; and
a thickness matching layer formed on the second-type work function layer, the thickness matching layer having a thickness roughly equal to a thickness of the first-type work function layer; and
an inter-device connection that connects the first semiconductor device and the second semiconductor device, comprising portions of the first-type work function layer, the second-type work function layer, and the thickness matching layer.

13. The integrated chip of claim 12 , wherein the first semiconductor device further comprises a scavenging layer on the second-type work function layer and wherein the second semiconductor device further comprises a scavenging layer between the second-type work function layer and the thickness matching layer.

14. The integrated chip of claim 13 , wherein the thickness matching layer comprises a material selected from the group consisting of titanium nitride, cobalt, and tungsten.

15. An integrated chip, comprising:
a first semiconductor device, comprising:
a semiconductor channel;
a first-type work function layer formed on the semiconductor channel;
a second-type work function layer formed on the first-type work function layer; and
a scavenging layer on the second-type work function layer; and

a second semiconductor device, comprising:
a semiconductor channel;
a second-type work function layer formed on the semiconductor channel;
a scavenging layer on the second-type work function layer; and
a thickness matching layer formed on the scavenging layer, the thickness matching layer having a thickness roughly equal to a thickness of the first-type work function layer.

16. The integrated chip of claim 15 , further comprising an inter-device connection that connects the n-type transistor and the p-type transistor, said inter-device connection comprising portions of the first-type work function layer, the second-type work function layer, and the thickness matching layer.

17. The integrated chip of claim 15 , wherein the first semiconductor device is an n-type transistor and wherein the second semiconductor device is a p-type transistor.

Assignees

• IBM

Inventors

• Bao Ruqiang
• Bi Zhenxing
• Lee Choonghyun
• Xu Zheng

Classifications

• H01L29/7803

  Electricity · mapped topic

• H01L27/092 Primary

  Electricity · mapped topic

• H01L21/823885

  Electricity · mapped topic

• H01L27/0652

  Electricity · mapped topic

• H01L29/78642

  Electricity · mapped topic