Semiconductor packages including indicators for evaluating a distance and methods of calculating the distance

Patent metadata

Field	Value
Publication number	US-10312196-B2
Application number	US-201815945989-A
Country	US
Kind code	B2
Filing date	Apr 5, 2018
Priority date	Jul 17, 2017
Publication date	Jun 4, 2019
Grant date	Jun 4, 2019

Abstract

A semiconductor package may include a package substrate to which a first semiconductor chip is attached, an encapsulant covering the first semiconductor chip, and an indicator disposed within the semiconductor package. A side surface of the indicator is exposed at a side surface of the semiconductor package, and a width of a vertical section of the indicator parallel with the exposed side surface of the indicator varies as the vertical section of the indicator becomes farther from the side surface of the semiconductor package.

First claim

What is claimed is:

1. A semiconductor package comprising:
a package substrate to which a first semiconductor chip is attached;
an encapsulant covering the first semiconductor chip; and
an indicator including an array of indicating blocks disposed within the semiconductor package,
wherein at least one of the indicating blocks is exposed at a side surface of the semiconductor package, and
wherein the number of the indicating blocks exposed by a vertical section of the indicator parallel with the side surface of the semiconductor package varies as the vertical section of the indicator becomes farther from the side surface of the semiconductor package.

2. The semiconductor package of claim 1 , wherein the indicator is disposed in the package substrate.

3. The semiconductor package of claim 1 , wherein the indicator is disposed on the package substrate.

4. The semiconductor package of claim 1 , wherein the indicating blocks are arrayed in a plurality of columns which are sequentially disposed from the side surface of the semiconductor package toward the first semiconductor chip.

5. The semiconductor package of claim 4 , wherein the indicating blocks disposed in two adjacent columns among the plurality of columns are arrayed in a zigzag fashion along a length direction of the plurality of columns.

6. The semiconductor package of claim 4 , wherein the indicating blocks arrayed in each of the plurality of columns are spaced apart from each other by substantially the same distance.

7. The semiconductor package of claim 1 ,
wherein each of the indicating blocks includes a rectangular pattern; and
wherein the indicating blocks are substantially the same size.

8. The semiconductor package of claim 1 ,
wherein the indicating blocks are arrayed in first to third columns which are sequentially disposed from the side surface of the semiconductor package toward the first semiconductor chip; and
wherein the number of the indicating blocks arrayed in the first column, the number of the indicating blocks arrayed in the second column, and the number of the indicating blocks arrayed in the third column are different from each other.

9. The semiconductor package of claim 1 , wherein the number of the indicating blocks which are exposed at the side surface of the semiconductor package varies according a distance between the side surface of the semiconductor package and the first semiconductor chip.

10. The semiconductor package of claim 1 , wherein the indicating blocks are disposed between the encapsulant and the package substrate.

11. The semiconductor package of claim 1 ,
wherein the package substrate includes interconnection patterns; and
wherein the indicating blocks are located at the same level as the interconnection structure.

12. The semiconductor package of claim 1 , further comprising a second semiconductor chip which is stacked on the first semiconductor chip and is offset from the first semiconductor chip.

13. The semiconductor package of claim 1 , further comprising:
an additional semiconductor chip disposed between the first semiconductor chip and the package substrate; and
a supporting part disposed between the first semiconductor chip and the package substrate to support the first semiconductor chip and to provide a cavity in which the additional semiconductor chip is disposed.

Assignees

• Sk Hynix Inc

Inventors

• Lee Sukwon
• Min Bok Gyu

Classifications

• H10P54/00

  Cutting or separating of wafers, substrates or parts of devices · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/291

  characterised by containers, encapsulations, or other housings for the stacked chips · CPC title

• H10W90/24

  at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape · CPC title

• H10W90/20

  Configurations of stacked chips · CPC title