Circuit substrate having noise suppression structure

US8994470B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-8994470-B2
Application numberUS-201214113187-A
CountryUS
Kind codeB2
Filing dateApr 25, 2012
Priority dateApr 28, 2011
Publication dateMar 31, 2015
Grant dateMar 31, 2015

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Abstract

Official abstract text for this publication.

A circuit substrate has three wiring layers, wherein a signal line is formed in a first wiring layer; a ground plane is formed in a second wiring layer; a resonant line is formed in a third wiring layer. A circumferential slit is formed in the ground plane, wherein an island electrode separated from the ground plane is formed inside the slit. The left end of the resonant line is connected to the island electrode through an interlayer-connecting via, while the right end of the resonant line is connected to the ground plane through an interlayer-connecting via. A transmission line (or a microstrip line) is formed using the signal line and the ground plane, and therefore a complex resonator is formed to embrace the transmission line. This achieves band elimination with regard to a signal component of a resonance frequency among signals propagating through the microstrip line. Thus, it is possible to form a noise suppression structure without mounting additional parts on the circuit substrate, and therefore it is possible to effectively eliminate power distribution noise and noise propagating through the signal line with a small and simple configuration.

First claim

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The invention claimed is: 1. A circuit substrate in which a transmission line is formed using a first conductor and a second conductor which are positioned opposite to each other in different wiring layers, the circuit substrate comprising: a circumferential slit formed in the second conductor; an island electrode which is formed inside the slit and which is separated from the second conductor; and a third conductor which is formed in a different wiring layer than the second c…

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What does patent US8994470B2 cover?
A circuit substrate has three wiring layers, wherein a signal line is formed in a first wiring layer; a ground plane is formed in a second wiring layer; a resonant line is formed in a third wiring layer. A circumferential slit is formed in the ground plane, wherein an island electrode separated from the ground plane is formed inside the slit. The left end of the resonant line is connected to th…
Who is the assignee on this patent?
Sakai Jun, Lenovo Innovations Ltd Hong Kong
What technology area does this patent fall under?
Primary CPC classification H01P7/08. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Mar 31 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).