Memory control circuit and memory test method

Patent metadata

Field	Value
Publication number	US-10311964-B2
Application number	US-201715598077-A
Country	US
Kind code	B2
Filing date	May 17, 2017
Priority date	Dec 27, 2016
Publication date	Jun 4, 2019
Grant date	Jun 4, 2019

Abstract

A memory control circuit, coupled to a multi-channel memory, includes a plurality of channel controllers coupled to respective channel memories of the multi-channel memory, and a built-in self-test (BIST) circuit. The BIST circuit includes a BIST controller and a plurality of command index registers which store respective command indexes related to the channel controllers. The BIST controller receives notification from at least two channel controllers of the channel controllers, which indicates that the at least two channel controllers complete respective current test commands. When the BIST controller arbitrates, the BIST controller selects at least a channel controller from the at least two channel controllers which send the notification, and sends respective next test command(s) to the selected at least one channel controller based on the respective command index(es) of the selected at least one channel controller.

First claim

What is claimed is:

1. A memory control circuit, coupled to a multi-channel memory, the multi-channel memory comprises a plurality of channel memories, the memory control circuit comprising:
a plurality of channel controllers, coupled to a respective one of a plurality of channel memories of the multi-channel memory; and
a built-in self-test (BIST) circuit, coupled to the channel controllers, the BIST circuit including a BIST controller and a plurality of command index registers, the BIST controller being coupled to the channel controllers, the command index registers being coupled to the BIST controller, the command index registers storing respective command indexes of the channel controllers, wherein
the BIST controller receives inform from at least two of the channel controllers which indicates that the informing at least two channel controllers already complete respective current test commands;
when the BIST controller arbitrates, the BIST controller selects at least one channel controller from the informing at least two channel controllers, and based on the respective command index(es) of the selected at least one channel controller, the BIST controller sends respective next test command(s) to the selected at least one channel controller,
the BIST controller determines whether the BIST controller is capable of concurrently sending the respective next test command(s) to the informing at least two channel controllers;
if the BIST controller determines that the BIST controller is capable of concurrently sending the respective next test command(s) to the informing at least two channel controllers, based on the respective command indexes of the informing at least two channel controllers, the BIST controller sends the respective next test command(s) to the informing at least two channel controllers and updates the respective command indexes of the informing at least two channel controllers; and
if the BIST controller determines that the BIST controller is not capable of concurrently sending the respective next test command(s) to the informing at least two channel controllers, the BIST controller selects at least m channel controller(s) among the informing at least two channel controllers, m being a maximum type number of the test commands that the BIST controller is allowed to concurrently send, and based on the respective command indexes of the selected at least m channel controller(s), the BIST controller sends the respective next test command(s) to the selected at least m channel controller(s) and updates the respective command index(es) of the selected at least m channel controller(s).

2. The memory control circuit according to claim 1 , wherein the BIST circuit further includes:
a receiving interface, coupled to the BIST controller, the receiving interface receiving a BIST command and sending to the BIST controller, the BIST controller selecting a test algorithm and generating a plurality of test commands based on the BIST command.

3. The memory control circuit according to claim 1 , wherein when the BIST circuit sends the respective next test command(s) to the selected at least m channel controller(s), the BIST controller updates the respective command index(es) stored in the respective command index register(s) corresponding to the selected at least m channel controller(s).

4. The memory control circuit according to claim 1 , wherein the BIST circuit further includes:
a plurality of data background generators, coupled to the BIST controller, the data background generators being for generating write data or expectation data; and
a plurality of comparators, coupled to the BIST controller and the data background generators, wherein
in executing a write test command, the data background generators generate the write data and send the write data to at least corresponding one of the channel controllers under control of the BIST controller; and
in executing a read test command, the data background generators generate the expectation data and the comparators compare read data from the channel controllers with the expectation data to decide whether a read test is passed or failed.

5. The memory control circuit according to claim 1 , wherein each of the channel controllers includes:
a command buffer, coupled to the BIST controller, for buffering a test command received by the channel controller;
a read data buffer, coupled to the BIST controller, for buffering read data from the channel controller;
a write data buffer, coupled to the BIST controller, for buffering write data when a write test command is executed; and
a finite state machine (FSM), coupled to the command buffer, the read data buffer, the write data buffer and the channel memory,
in executing a read test, based on a read test command of the command buffer, the FSM buffers read data from the channel memory in the read data buffer and the FSM informs the BIST controller and returns the read data back to the BIST controller; and
in executing a write test, based on a write test command of the command buffer, the FSM informs the BIST controller and the BIST controller sends the write data to the write data buffer.

6. The memory control circuit according to claim 1 , wherein the BIST controller determines that whether a type number of the respective current test commands completed by the at least two channel controllers is larger than m.

7. The memory control circuit according to claim 6 , wherein when the BIST controller determines that the type number of the respective current test commands completed by the at least two channel controllers is larger than m, the BIST controller sends to the selected at least m channel controller(s) of the at least two channel controllers the respective next test command(s) whose type number matches m.

8. The memory control circuit according to claim 7 , wherein a number of the selected at least m channel controller(s) is larger than or equal to m.

9. The memory control circuit according to claim 6 , wherein when the BIST controller determines that the type number of the respective current test commands completed by the at least two channel controllers is not larger than m, the BIST controller sends to the at least two channel controllers the respective next test command(s) whose type number matches the type number of the respective current test commands completed by the at least two channel controllers.

10. The memory control circuit according to claim 9 , wherein a number of the at least two channel controller is larger than or equal to the type number of the respective current test commands completed by the at least two channel controllers.

11. A multi-channel test method applied to a multi-channel memory coupled to a plurality of channel controllers, the multi-channel memory comprises a plurality of channel memories, the multi-channel test method comprising:
receiving inform from at least two of the channel controllers which indicates that the informing at least two channel controllers already complete respective current test commands; and
arbitrating and selecting at least one channel controller from the informing at least two channel controllers, and based on respective command index(es) of the selected at least one channel controller, sending respective next test command(s) to the selected at least one channel controller,
wherein the arbitrating step further includes:
determining whether concurrently sending the respective next test command(s) to the informing at least two channel controllers is capable or not;
if concurrently sending the respective next test command(s) to the informing at least two channel controllers is determined to be capable, based on the respective command index(es

Assignees

• Ind Tech Res Inst

Inventors

• Wu Kuan-Te
• Lai Jenn-Shiang
• Lo Chih-Yen
• Li Jin-Fu

Classifications

• G11C29/14 Primary

  Implementation of control logic, e.g. test mode decoders · CPC title

• G11C29/36

  Data generation devices, e.g. data inverters · CPC title

• G11C29/16

  using microprogrammed units, e.g. state machines · CPC title