Selective power state table composition

Patent metadata

Field	Value
Publication number	US-9679097-B2
Application number	US-201514608567-A
Country	US
Kind code	B2
Filing date	Jan 29, 2015
Priority date	Jan 31, 2014
Publication date	Jun 13, 2017
Grant date	Jun 13, 2017

Abstract

This application discloses a computing system to identify an interconnection between portions of a circuit design corresponding to different power domains. The computing system can select a subset of power state tables in the circuit design based, at least in part, on power supplies associated with the interconnection, and generate a composite power state table from the selected subset of power state tables. The computing system can analyze the interconnection to identify electrical characteristics based, at least in part, on power states in the composite power state table, and determine whether a power intent specification in the circuit design can prompt synthesis of interface circuitry capable of implementing the electrical characteristics for the interconnection.

First claim

The invention claimed is:

1. A method comprising:
identifying, by a computing device, an interconnection between portions of a circuit design corresponding to different power domains;
correlating, by the computing system, power state tables in the circuit design having power states that correspond to one or more shared power supplies associated with the interconnection;
utilizing, by the computing system, the correlated power state tables to select a subset of power state tables in the circuit design to combine into a composite power state table based, at least in part, on power supplies associated with the interconnection; and
analyzing, by the computing system, the interconnection between the portions of the circuit design corresponding to the different power domains based, at least in part, on power states in the composite power state table.

2. The method of claim 1 , wherein analyzing the interconnection further comprises:
identifying electrical characteristics for the interconnection based, at least in part, on power states in the composite power state table; and
determining whether a power intent specification in the circuit design is configured to prompt synthesis of interface circuitry capable of implementing the identified electrical characteristics.

3. The method of claim 2 , wherein the interface circuitry is configured to electrical isolate the portions of the circuit design corresponding to the different power domains or to level shift a voltage exchanged between the portions of the circuit design corresponding to the different power domains.

4. The method of claim 2 , further comprising issuing, by the computing system, an error message when the power intent specification in the circuit design fails to specify interface circuitry that implements the identified electrical characteristics.

5. The method of claim 1 , wherein correlating the power state tables further comprises generating a dependence graph that defines relationships between the power supply tables according to their shared power supplies to provide a minimal subset of the power state tables in the circuit design to combine into the composite power state table.

6. The method of claim 1 , further comprising:
identifying, by the computing system, one or more power state tables having an unreachable power state or an undetermined power state; and
generating, by the computing system, the composite power state table from the selected subset of power state tables in the circuit design, wherein power states from the composite power state table corresponding to the unreachable power state or the undetermined power state are excluded from the composite power state table.

7. An apparatus comprising at least one computer-readable memory device storing instructions configured to cause one or more processing devices to perform operations comprising:
comparing power states of multiple power state tables in a power intent specification of a circuit design;
identifying one or more power state tables having an unreachable power state or an undetermined power state based on the comparison;
correlating the power state tables in the circuit design having power states that correspond to one or more shared power supplies;
utilizing the correlated power state tables to select a subset of the power state tables in the circuit design to combine into a composite power state table having power states that correspond to a group of power supplies, while excluding power states corresponding to the unreachable power state or the undetermined power state; and
performing power state analysis on a portion of the circuit design associated with the group of power supplies based, at least in part, on the composite power state table.

8. The apparatus of claim 7 , wherein the instructions are configured to cause one or more processing devices to perform operations further comprising issuing an error message to identify the power state tables having the unreachable power state or the undetermined power state.

9. The apparatus of claim 7 , wherein performing power state analysis on a portion of the circuit design associated with the group of power supplies further comprising:
identifying electrical characteristics for the portion of the circuit design based, at least in part, on the power states in the composite power state table; and
determining whether a power intent specification in the circuit design is configured to prompt synthesis of circuitry capable of implementing the identified electrical characteristics.

10. The apparatus of claim 9 , wherein the circuitry is configured to electrical isolate the portion of the circuit design or to level shift voltage exchanged in the portion of the circuit design.

11. The apparatus of claim 7 , wherein the portion of the circuit design corresponds to an interconnection between circuitry in different power domains of the circuit design.

12. An apparatus comprising at least one computer-readable memory device storing instructions configured to cause one or more processing devices to perform operations comprising:
correlating power state tables in a circuit design having power states that correspond to one or more shared power supplies;
utilizing the correlated power state tables to select a subset of the power state tables in the circuit design to combine into a composite power state table having power states that correspond to a group of power supplies; and
performing power state analysis on a portion of the circuit design associated with the group of power supplies by identifying electrical characteristics for a portion of the circuit design based, at least in part, on the power states in the composite power state table, and determining whether a power intent specification in the circuit design is configured to prompt synthesis of circuitry capable of implementing the identified electrical characteristics.

13. The apparatus of claim 12 , wherein the circuitry is configured to electrical isolate the portion of the circuit design or to level shift voltage exchanged in the portion of the circuit design.

14. The apparatus of claim 12 , wherein correlating power state tables in the circuit design further comprises generating a dependence graph identifying each power state table and any corresponding relationships with other power state tables based on the shared power supplies to provide a minimal subset of the power state tables in the circuit design to combine into the composite power state table.

15. The apparatus of claim 12 , wherein the portion of the circuit design corresponds to an interconnection between circuitry in different power domains of the circuit design.

16. The apparatus of claim 12 , wherein the instructions are configured to cause one or more processing devices to perform operations further comprising combining the selected subset of the power state tables into the composite power state table.

17. The apparatus of claim 12 , wherein selecting the subset of the power state tables in the circuit design to combine into the composite power state table is performed when at least one of the power state tables in the circuit design does not include power states corresponding to the group of power supplies.

Assignees

• Mentor Graphics Corp

Inventors

• Srivastava Amit

Classifications

• G06F30/398 Primary

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• G06F2119/06

  Power analysis or power optimisation · CPC title

• G06F17/5081 Primary

  Physics · mapped topic

• G06F2217/78

  Physics · mapped topic