Predicting semiconductor package warpage

Patent metadata

Field	Value
Publication number	US-10309884-B2
Application number	US-201715627514-A
Country	US
Kind code	B2
Filing date	Jun 20, 2017
Priority date	Mar 30, 2015
Publication date	Jun 4, 2019
Grant date	Jun 4, 2019

Abstract

A method for predicting the electrical functionality of a semiconductor package, the method includes performing a first stiffness test for a first semiconductor package, receiving failure data for the first semiconductor package, the failure data includes results of an electrical test performed after the first semiconductor package is assembled on a printed circuit board, generating a database comprising results of the first stiffness test as a function of the failure data for the first semiconductor package, performing a second stiffness test for a second semiconductor package, identifying a unique result from the results of the first stiffness test in the database, the unique result aligns with a result of the second stiffness test, and predicting a failure data for the second semiconductor package based on the failure data for the first semiconductor package which corresponds to the unique result of the first stiffness test identified in the database.

First claim

What is claimed is:

1. A method of predicting warpage of a semiconductor package comprising:
performing a stiffness test comprising:
stabilizing a portion of the semiconductor package in a fixture, such that a cantilevered portion of the semiconductor package remains unstabilized,
applying a force to a corner of the cantilevered portion causing the semiconductor package to bend,
measuring the applied force, and
measuring a deflection of the corner of the cantilevered portion;

recording stiffness test results comprising the applied force as a function of the deflection of the corner; and
using the stiffness test results to predict the warpage of the semiconductor package.

2. The method of claim 1 , wherein stabilizing the portion of the semiconductor package comprises:
stabilizing half of the semiconductor package defined by a diagonal line extending between two corners of the semiconductor package.

3. The method of claim 1 , wherein the stiffness test is carried out in a temperature controlled chamber, and the temperature of the temperature controlled chamber is recorded along with the stiffness test results.

4. The method of claim 1 , wherein a static testing machine is used to apply the force, measure the applied force, and measure the deflection of the corner.

5. The method of claim 1 , wherein recording stiffness test results comprises:
recording properties of the semiconductor package comprising at least one of laminate size, die size, lid shape, lid material, laminate composition, sealant material, and amount of sealant used.

6. The method of claim 5 , further comprising:
using the stiffness test results to predict warpage of another semiconductor package by comparing the properties of the semiconductor package and properties of the other semiconductor package.

7. The method of claim 1 , further comprising:
repeating the stiffness test at least once for each corner of the semiconductor package.

8. A method, comprising:
performing a stiffness test of a semiconductor package, the stiffness test comprising:
stabilizing half of the semiconductor package in a fixture, such that an unstabilized half of the semiconductor package remains free to move,
applying a force to a corner of the unstabilized half of the semiconductor package causing the semiconductor package to bend,
measuring the amount of applied force, and
measuring the amount of deflection of the corner of the unstabilized half of the semiconductor package;

recording stiffness test results comprising the amount of applied force and the amount of deflection of the corner;
assembling the semiconductor package on a printed circuit board;
performing electrical testing of the semiconductor package after the semiconductor package is assembled on a printed circuit board, the electrical testing generating failure data; and
generating a database comprising results of the stiffness test for the semiconductor package and the failure data for the semiconductor package.

9. The method of claim 8 , wherein half of the semiconductor package is defined by a diagonal line extending between two corners of the semiconductor package.

10. The method of claim 8 , wherein the stiffness test is carried out in a temperature controlled chamber, and the temperature of the temperature controlled chamber is recorded along with the stiffness test results.

11. The method of claim 8 , wherein a static testing machine is used to apply the force, measure the applied force, and measure the amount of deflection of the corner.

12. The method of claim 8 , further comprising:
correlating the amount of applied force and the amount of deflection of the corner to predict warpage of the semiconductor package.

13. The method of claim 12 , wherein the results of the stiffness test comprises:
properties of the semiconductor package comprising at least one of laminate size, die size, lid shape, lid material, laminate composition, sealant material, and amount of sealant used.

14. The method of claim 13 , further comprising:
using the stiffness test results to predict warpage of another semiconductor package by comparing the properties of the semiconductor package and properties of the other semiconductor package.

15. The method of claim 8 , further comprising:
repeating the stiffness test at least once for each corner of the semiconductor package.

16. A method, comprising:
performing a stiffness test of a semiconductor package, the stiffness test comprising:
stabilizing a portion of the semiconductor package in a fixture, such that a cantilevered portion of the semiconductor package remains free to move,
applying a force to a corner of the cantilevered portion of the semiconductor package causing the semiconductor package to bend,
measuring the amount of force applied to the corner of the cantilevered portion of the semiconductor package, and
measuring the amount of deflection of the corner of the cantilevered portion;

correlating the amount of force applied to the corner of the cantilevered portion and the amount of deflection of the corner of the cantilevered portion as results of the stiffness test for the semiconductor package; and
using the results of the stiffness test to predict warpage of the semiconductor package.

17. The method of claim 16 , wherein stabilizing the portion of the semiconductor package comprises:
stabilizing half of the semiconductor package defined by a diagonal line extending between corners of the semiconductor package.

18. The method of claim 16 , further comprising:
recording the results of the stiffness test in a database; and
recording properties of the semiconductor package comprising at least one of laminate size, die size, lid shape, lid material, laminate composition, sealant material, and amount of sealant used.

19. The method of claim 16 , further comprising:
assembling the semiconductor package on a printed circuit board; and
performing electrical testing of the semiconductor package after the semiconductor package is assembled on a printed circuit board, the electrical testing generating failure data for the semiconductor package.

20. The method of claim 19 , further comprising:
generating a database comprising results of the stiffness test for the semiconductor package and the failure data for the semiconductor package.

Assignees

• IBM

Inventors

• Ayotte Stephen P
• Liniger Eric G
• Longenbach Travis S

Classifications

• G01N2033/0078

  Physics · mapped topic

• G01N3/42 Primary

  by performing impressions under a steady load by indentors, e.g. sphere, pyramid (G01N3/54 takes precedence) · CPC title

• G01M5/0075 Primary

  by means of external apparatus, e.g. test benches or portable test systems (G01M5/005 takes precedence) · CPC title

• G01N3/20

  by applying steady bending forces (G01N3/26, G01N3/28 take precedence) · CPC title

• G01R31/2896

  Testing of IC packages; Test features related to IC packages (containers per se H10W76/10, encapsulations per se H10W74/00) · CPC title