Display panel, array substrate, and fabrication method thereof

Patent metadata

Field	Value
Publication number	US-10304875-B2
Application number	US-201715492035-A
Country	US
Kind code	B2
Filing date	Apr 20, 2017
Priority date	Dec 13, 2016
Publication date	May 28, 2019
Grant date	May 28, 2019

Abstract

The disclosure provides a display panel, an array substrate and a fabrication method thereof. The fabrication method of the array substrate includes forming a plurality of first thin film transistors and a plurality of second thin film transistors on the first substrate. The etch stopper layer of the second thin film transistor is different from an etch stopper layer of the first thin film transistor, and a threshold voltage of the second thin film transistor is higher than a threshold voltage of the first thin film transistor. By using the disclosed thin film transistors to form the gate driving circuit, the second thin film transistor with a high threshold voltage can be used as the driving signal outputting transistor. The abnormal multi-pulse of the gate driving circuit and the display panel caused by the low threshold voltage of the second thin film transistors may be therefore avoided.

First claim

What is claimed is:

1. A method for fabricating an array substrate, comprising:
providing a first substrate; and
forming a plurality of first thin film transistors and a plurality of second thin film transistors on the first substrate, wherein:
each of the plurality of first thin film transistors includes a first oxide semiconductor layer formed over a first gate electrode, and a first etch stop layer and a second etch stop layer together formed over the first oxide semiconductor layer, wherein the first etch stop layer partially covers the first oxide semiconductor layer, the second etch stop layer encapsulates the first etch stop layer and partially covers the first oxide semiconductor layer, with a surface of the first oxide semiconductor layer located on two sides of the second etch stop layer exposed,
each of the plurality of second thin film transistors includes a second oxide semiconductor layer formed over a second gate electrode, and another second etch stop layer formed over the second oxide semiconductor layer, wherein the another second etch stop layer partially covers the second oxide semiconductor layer, with a surface of the second oxide semiconductor layer located on two sides of the another second etch stop layer exposed,
the second etch stop layer and the another second etch stop layer are different from the first etch stop layer, and
a threshold voltage of the second thin film transistor is higher than a threshold voltage of the first thin film transistor.

2. The method for fabricating an array substrate according to claim 1 , wherein the first substrate comprises a display region and a function region, after forming the plurality of first thin film transistors and the plurality of second thin film transistors on the first substrate, further comprising:
forming a pixel driving layer by using the thin film transistors located in the display region, the pixel driving layer comprising a plurality of gate lines arranged along a first direction, a plurality of data lines arranged along a second direction, and the first thin film transistors located at a region defined by the gate lines and the data lines;
forming a gate driving circuit by using the thin film transistors located in the function region.

3. The method for fabricating an array substrate according to claim 2 , wherein
the thin film transistors located in the display region comprise at least one first thin film transistor; and
the thin film transistors in the gate driving circuit comprise at least one second thin film transistor.

4. The method for fabricating an array substrate according to claim 1 , wherein forming the plurality of first thin film transistors and the plurality of second thin film transistors comprises:
forming a plurality of first gate electrodes and a plurality of second gate electrodes on the first substrate;
forming a gate insulating layer on the plurality of first gate electrodes and the plurality of second gate electrodes;
forming a plurality of first oxide semiconductor layers on the gate insulating layer opposite to the first substrate corresponding to a position of the first gate electrodes, and forming a plurality of second oxide semiconductor layers on the gate insulating layer opposite to the first substrate corresponding to a position of the second gate electrodes;
forming a plurality of first etch stop layers on the plurality of first oxide semiconductor layers, the plurality of first etch stop layers partially covering the plurality of first oxide semiconductor layers;
forming a plurality of second etch stop layers on the plurality of first oxide semiconductor layers covered by the plurality of first etch stop layers and on the plurality of second oxide semiconductor layers; and
forming source electrodes, drain electrodes and passivation layers of the plurality of first thin film transistors and the plurality of second thin film transistors, wherein:
for each of the plurality of first thin film transistors, a source electrode and a drain electrode are individually located on two sides of the second etch stop layer and partially cover the second etch stop layer, and projections of the source electrode and the drain electrode onto the first substrate at least partially overlap with the first gate electrode,
for each of the plurality of second thin film transistors, a source electrode and a drain electrode are individually located on two sides of the another second etch stop layer and partially cover the another second etch stop layer, and projections of the source electrode and the drain electrode onto the first substrate at least partially overlap with the second gate electrode, and
the passivation layers cover the source electrodes, the drain electrodes, the plurality of second etch stop layers and the gate insulating layer.

5. The method for fabricating an array substrate according to claim 4 , wherein a material of the plurality of first etch stop layers is different from a material of the plurality of second etch stop layers, and/or a thickness of the plurality of first etch stop layers is different from a thickness of the plurality of second etch stop layers.

6. The method for fabricating an array substrate according to claim 5 , wherein the thickness of the plurality of second etch stop layers is approximately 20 nm-400 nm including the endpoint values, and a thickness difference between an etch stop layer of the first thin film transistor and an etch stop layer of the second thin film transistor is approximately 10 nm-300 nm including the endpoint values.

7. The method for fabricating an array substrate according to claim 4 , after forming the plurality of first etch stop layers on the plurality of first oxide semiconductor layers, and before forming the plurality of second etch stop layers on the plurality of second oxide semiconductor layers, further comprising:
performing a surface plasma treatment to the plurality of second oxide semiconductor layers.

8. The method for fabricating an array substrate according to claim 7 , wherein the plurality of first etch stop layers and the plurality of second etch stop layers are formed by a same process or by different processes.

9. The method for fabricating an array substrate according to claim 8 , wherein a film-forming power of the plurality of first etch stop layers is lower than a film-forming power of the plurality of second etch stop layers, or a film-forming temperature of the plurality of first etch stop layers is higher than a film-forming temperature of the plurality of second etch stop layers, or a film-forming pressure of the plurality of first etch stop layers is lower than a film-forming pressure of the plurality of second etch stop layers, or when the plurality of first and second etch stop layers are silicon dioxide, a silane flow of a film-forming process of the plurality of first etch stop layers is higher than a silane flow of a film-forming process of the plurality of second etch stop layers.

Assignees

• Shanghai Tianma Micro Elect Co
• Tianma Micro Electronics Co Ltd

Inventors

• Lou Junhui
• Wu Tianyi

Classifications

• H10P95/70

  Chemical treatments · CPC title

• H10P52/00

  Grinding, lapping or polishing of wafers, substrates or parts of devices · CPC title

• H10P50/20

  Dry etching; Plasma etching; Reactive-ion etching · CPC title

• H01L27/127 Primary

  Electricity · mapped topic

• H01L21/465

  Electricity · mapped topic