Time-to-digital converter

Patent metadata

Field	Value
Publication number	US-10303124-B2
Application number	US-201815985252-A
Country	US
Kind code	B2
Filing date	May 21, 2018
Priority date	Feb 3, 2015
Publication date	May 28, 2019
Grant date	May 28, 2019

Abstract

A time-to-digital converter includes: an input for receiving a time-domain input signal; an output for providing a digital output signal; a time register coupled to the input and to a first node; a time quantizer coupled to the time register for providing the digital output signal at the output; and a digital-to-time converter coupled to the output for providing a feed-back signal at the first node.

First claim

What is claimed is:

1. A cascaded time-to-digital converter (TDC) comprising:
a first first-order TDC for receiving a input signal, wherein the first first-order TDC is a first-order TDC of a plurality of first-order TDCs;
a second first-order TDC configured to receive as input a first time quantization error produced by the first first-order TDC, wherein the second first-order TDC is a first-order TDC of the plurality of first-order TDCs; and
a combiner circuit coupled to an output of the first first-order TDC and an output of the second first-order TDC, wherein the combiner circuit is configured to produce a digital output signal by combining the output of the first first-order TDC and the output of the second first-order TDC.

2. The cascaded time-to-digital converter of claim 1 , wherein the second first-order TDC is configured to produce a second time quantization error, wherein the second time quantization error is fed to another one of the plurality of first-order TDCs other than the first first-order TDC to form a MASH 1-1-1 structure.

3. The cascaded time-to-digital converter of claim 1 , wherein each first-order TDC in the plurality of first-order TDCs includes:
an output coupled to the combiner circuit;
a time register coupled a first node;
a time quantizer coupled to the time register for providing a digital output signal at the output; and
a digital-to-time converter coupled to the output for providing a feedback signal at the first node.

4. The cascaded time-to-digital converter of claim 3 , wherein each first-order TDC in the plurality of first-order TDCs further includes:
an input, wherein the time register is further coupled to the input.

5. The cascaded time-to-digital converter of claim 3 ,
wherein the first quantization error signal is input at a first node of the first first-order TDC as a feedback signal.

6. The cascaded time-to-digital converter of claim 3 ,
wherein the digital-to-time converter of the first first-order TDC is coupled to the time register for delaying an output signal of the time register in response to the digital output signal.

7. The cascaded time-to-digital converter of claim 1 ,
wherein the first first-order TDC is further configured to combine the input signal with the first quantization error signal to produce a modified time-domain input signal.

8. The cascaded time-to-digital converter of claim 7 ,
wherein a time register of the first first-order TDC is configured to delay the modified time-domain input signal by at least one cycle of a sampling clock.

9. The cascaded time-to-digital converter of claim 7 ,
wherein the digital output signal is a digital representation of the time-domain input signal including a noise-shaped quantization error.

10. The cascaded time-to-digital converter of claim 1 ,
wherein the input signal comprises a first digital clock and a second digital clock.

11. The cascaded time-to-digital converter of claim 10 ,
wherein a value of the input signal corresponds to a time difference between a transition of the first digital clock and a transition of the second digital clock.

12. A cascaded time-to-digital converter comprising:
a first node coupled to an input line for receiving an input signal;
an output for providing a digital output signal;
a time register coupled the first node; and
a digital-to-time converter coupled to the output for providing a feedback signal at the first node, wherein the digital-to-time converter is further coupled to the time register for delaying an output signal of the time register in response to the digital output signal.

13. The time-to-digital converter of claim 12 , wherein the feedback signal is a quantization error signal.

14. The time-to-digital converter of claim 12 , wherein the time register is further configured to combine the input signal with the quantization error signal to produce a modified time-domain input signal.

15. The time-to-digital converter of claim 14 , wherein the time register is configured to delay the modified time-domain input signal by at least one cycle of a sampling clock.

16. The time-to-digital converter of claim 12 , wherein the input signal comprises a first digital clock and a second digital clock.

17. The cascaded time-to-digital converter of claim 16 , wherein a value of the input signal corresponds to a time difference between a transition of the first digital clock and a transition of the second digital clock.

18. A method for time-to-digital conversion of an input signal, the method comprising:
receiving a time-domain input signal;
buffering, in a time register, a first signal derived from the time-domain input signal and a feedback signal;
time-quantizing the first signal for providing a digital output signal; and
digital-to-time converting the digital output signal for providing the feedback signal; and
delaying an output signal of the time register in response to the digital output signal.

19. The method according to claim 18 , further comprising:
combining the input signal with the feedback signal to produce a modified time-domain input signal.

20. The method according to claim 18 , further comprising:
delaying the modified time-domain input signal by at least one cycle of a sampling clock.

Assignees

• Huawei Tech Co Ltd

Inventors

• Wu Ying
• Staszewski Robert Bogdan
• Mao Yihong

Classifications

• G04F10/005 Primary

  Time-to-digital converters [TDC] (analog-to-digital converters with intermediate conversion to time or phase H03M1/50, H03M1/60) · CPC title

• H03M3/414

  having multiple quantisers arranged in cascaded loops, each of the second and further loops processing the quantisation error of the loop preceding it, i.e. multiple stage noise shaping [MASH] type · CPC title