1-16 and 1.5-7.5 frequency divider for clock synthesizer in digital systems

Patent metadata

Field	Value
Publication number	US-10298382-B2
Application number	US-201715673298-A
Country	US
Kind code	B2
Filing date	Aug 9, 2017
Priority date	Jun 23, 2016
Publication date	May 21, 2019
Grant date	May 21, 2019

Abstract

A frequency divider unit has a digital frequency divider configured to divide by an odd integer, and a dual-edge-triggered one-shot coupled to double frequency of an output of the digital frequency divider. The frequency divider unit is configurable to divide an input frequency by a configurable ratio selectable from at least non-integer ratios of 1.5, 2.5, and 3.5. In embodiments, the frequency divider unit relies on circuit delays to determine an output pulsewidth, and in other embodiments the output pulsewidth is determined from a clock signal. In embodiments, the unit is configurable to divide an input frequency by a configurable ratio selectable from at least non-integer ratios of 1.5, 2.5, 3.5, 4.5, 5.5, 6.5, and 7.5 as well as many integer ratios including 2, 4, 6, and 8. In embodiments, the digital frequency divider is configurable to provide a 50% duty cycle to the one-shot.

First claim

What is claimed is:

1. A divider system configured with gated clocks having a divider system output, the divider system comprising:
a first divider configured to divide by a selectable divide ratio of five, seven, or nine and having a square-wave output;
the first divider coupled to drive a frequency doubler coupled to drive an output with pulses having width determined from edges of a digital clock;
the frequency doubler comprising:
a first flipflop having a data input coupled to receive an output of the first divider and configured to trigger on a rising edge of the digital clock;
a second flipflop having a data input coupled to receive a data input, and coupled to receive the output of the first divider and configured to trigger on a falling edge of the digital clock; and
an exclusive-or gate coupled to receive an output from the first flipflop and an output from the second flipflop;
a divide-by-3 divider having square-wave output and coupled to drive a second frequency doubler;
a gated clock tree coupled to provide a gated clock to a selected one of the first divider and the divide-by-three divider, an unselected one of the first divider and the divide-by-three divider receiving a quiescent clock; and
multiplexing circuitry adapted to select the divider system output from at least an output of the divide-by-3 divider, an output of the second frequency doubler, and an output of the first divider.

2. The divider system of claim 1 wherein the second frequency doubler comprises:
a first flipflop having a data input coupled to receive an output of the divide-by-three divider and configured to trigger on a rising edge of an output of the gated clock tree;
a second flipflop having a data input coupled to receive a data input, and coupled to receive the output of the divide-by-three divider and configured to trigger on a falling edge of the output of the gated clock tree; and
an exclusive-or gate coupled to receive an output from the first flipflop and an output from the second flipflop.

3. A frequency divider system comprising:
a first digital frequency divider configurable to divide by an odd integer and having a square-wave output; and
a dual-edge-triggered one-shot coupled to double frequency of the square wave output of the first digital frequency divider;
wherein the frequency divider system is configurable to divide an input frequency by a configurable ratio selectable from at least non-integer ratios of 1.5, 2.5, and 3.5.

4. The frequency divider of claim 3 , wherein the dual-edge-triggered one-shot relies on circuit delays to determine a pulsewidth.

5. The frequency divider of claim 4 wherein, the frequency divider is configurable such that the dual edge-triggered one-shot receives an output of a divide-by-N stage having 50% duty cycle, where N an odd integer selectable from a group comprising at least 3 and 5.

6. A frequency divider of claim 5 further comprising a phase detector coupled through a filter to a voltage controlled oscillator (VCO), to form a phase locked loop clock synthesis subsystem.

7. The frequency divider of claim 4 wherein, the frequency divider is configurable to divide the input frequency by a configurable ratio selectable from at least non-integer ratios of 1.5, 2.5, 3.5, 4.5, 5.5, 6.5, and 7.5.

8. The frequency divider of claim 7 , wherein the frequency divider is configurable to divide the input frequency by a configurable ratio selectable from a plurality of integer ratios including 2, 4, 6, and 8 as well as the non-integer ratios.

9. The frequency divider of claim 3 , wherein the dual-edge-triggered one-shot is a digital one-shot where a pulsewidth is determined from a clock signal.

10. The frequency divider of claim 9 , wherein the frequency divider is configurable to divide the input frequency by a configurable ratio selectable from at least non-integer ratios of 1.5, 2.5, 3.5, 5.5, 6.5, and 7.5.

11. The frequency divider of claim 9 , wherein the frequency divider is configurable such that the dual edge-triggered one-shot receives an output of a divide-by-N stage having 50% duty cycle, where N an odd integer selectable from a group comprising at least 3 and 5.

12. The frequency divider of claim 11 , wherein the configurable ratio selectable from at least non-integer ratios of 1.5, 2.5, 3.5, 4.5, 5.5, 6.5, and 7.5 is further selectable from a plurality of integer ratios including 2, 4, 6, and 8.

13. A frequency divider of claim 9 further comprising a phase detector coupled through a filter to a voltage controlled oscillator (VCO), to form a phase locked loop clock synthesis subsystem.

14. A method of dividing an input frequency by a non-integer ratio selectable from a group comprising at least non-integer ratios of 1.5, 2.5, and 3.5 to provide an output, comprising:
dividing a clock signal by an odd integer to produce an intermediate signal frequency; and
multiplying the intermediate signal frequency by two wherein the intermediate frequency has square wave waveform a pulse width of the output is determined by circuit delays in a one-shot circuit triggered by both rising and falling edges of the intermediate frequency.

15. The method of claim 14 , wherein a pulse width of the output is determined from a clock signal.

Assignees

• Omnivision Tech Inc

Inventors

• Wu Charles Qingle
• Niu Qi

Classifications

• H03L7/0991

  the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider (H03L7/0995 takes precedence; fixed oscillators with means for selecting among various phases H03L7/0814) · CPC title

• H03C3/0933

  using fractional frequency division in the feedback loop of the phase locked loop · CPC title

• G06F1/08 Primary

  Clock generators with changeable or programmable clock frequency · CPC title

• H03L7/18

  using a frequency divider or counter in the loop (H03L7/20, H03L7/22 take precedence) · CPC title

• G11B20/1423

  Code representation depending on subsequent bits, e.g. delay modulation, double density code, Miller code · CPC title