Wiring pattern manufacturing method and transistor manufacturing method

Patent metadata

Field	Value
Publication number	US-10297773-B2
Application number	US-201615156958-A
Country	US
Kind code	B2
Filing date	May 17, 2016
Priority date	Nov 21, 2013
Publication date	May 21, 2019
Grant date	May 21, 2019

Abstract

A wiring pattern manufacturing method includes: applying a liquid body including a first formation material on a substrate to form a base film; applying a liquid body including a second formation material on at least part of a surface of the base film to form a protection layer of the base film; forming a resist layer on a surface of the protection layer to expose the resist layer with desired patterning light; causing the exposed resist layer to come into contact with a developer to remove the resist layer and the protection layer until the base film is uncovered corresponding to the patterning light; and after depositing a catalyst on a surface of the uncovered base film, causing an electroless plating solution to come into contact with the surface of the base film to perform electroless plating.

First claim

What is claimed is:

1. A transistor manufacturing method comprising:
forming a gate electrode on a substrate;
forming an insulator layer on the gate electrode to cover the gate electrode; and
forming a source electrode and a drain electrode on the insulator layer,
wherein the forming the source electrode and the drain electrode comprises:
applying a liquid body including a first formation material on at least part of the insulator layer to form a plating base film;
applying a liquid body including a second formation material on at least part of a surface of the plating base film to form a protection layer of the plating base film;
forming a photoresist layer that includes a photoresist material on a surface of the protection layer to expose the photoresist layer with desired patterning light;
causing the exposed photoresist layer to come into contact with a developer to remove the photoresist layer and the protection layer to form an uncovered portion of the plating base film corresponding to the patterning light; and
after depositing a metal as a catalyst for electroless plating on a surface of the uncovered portion of the plating base film, causing an electroless plating solution to come into contact with the catalyst on the surface of the uncovered portion of the plating base film to perform electroless plating,
wherein the first formation material is a silane coupling agent that includes a group having at least one of a nitrogen atom and a sulfur atom.

2. The transistor manufacturing method according to claim 1 , wherein
the second formation material has smaller solubility in the developer than the first formation material.

3. The transistor manufacturing method according to claim 1 , wherein
the second formation material is an organic silicon compound having a hydrolysis group that is bonded to a silicon atom.

4. The transistor manufacturing method according to claim 3 , wherein
the second formation material is an organic silicon compound having one hydrolysis group that is bonded to the silicon atom.

5. The transistor manufacturing method according to claim 3 , wherein
the second formation material is an organic silicon compound having two or three hydrolysis groups that are bonded to the silicon atom.

6. The transistor manufacturing method according to claim 1 , wherein
the silane coupling agent has an amino group.

7. The transistor manufacturing method according to claim 6 , wherein
the silane coupling agent is a primary amine or a secondary amine.

8. The transistor manufacturing method according to claim 1 , wherein
the substrate is made of a non-metallic material.

9. The transistor manufacturing method according to claim 8 , wherein
the substrate is made of a resin material.

10. The transistor manufacturing method according to claim 9 , wherein
the substrate has flexibility.

11. The transistor manufacturing method according to claim 9 , wherein
the plating base film is formed by a heat treatment at a heating temperature that is lower than a deformation temperature of the substrate.

12. A method for manufacturing a transistor, the method comprising:
applying a liquid body including a first formation material on at least part of a substrate to form a plating base film;
applying a liquid body including a second formation material on at least part of a surface of the plating base film to form a protection layer of the plating base film;
forming a photoresist layer that includes a photoresist material on a surface of the protection layer to expose the photoresist layer with desired patterning light;
causing the exposed photoresist layer to come into contact with a developer to remove the photoresist layer and the protection layer to form an uncovered portion of the plating base film corresponding to the patterning light; and
after depositing a metal as a catalyst for electroless plating on a surface of the uncovered portion of the plating base film, causing an electroless plating solution to come into contact with the catalyst on the surface of the uncovered portion of the plating base film to perform electroless plating to form a gate electrode,
wherein the first formation material is a silane coupling agent that includes a group having at least one of a nitrogen atom and a sulfur atom, and
wherein the second formation material is an organic silicon compound.

Assignees

• Nikon Corp

Inventors

• Koizumi Shohei
• Sugizaki Takashi
• Kawakami Yusuke

Classifications

• C23C18/32

  Coating with nickel, cobalt or mixtures thereof with phosphorus or boron (C23C18/50 takes precedence) · CPC title

• C23C18/1651

  Two or more layers only obtained by electroless plating · CPC title

• C23C18/34

  using reducing agents · CPC title

• H01L51/0005

  Electricity · mapped topic

• C23C18/42

  Coating with noble metals · CPC title