Nanosheet transistor with uniform effective gate length

Patent metadata

Field	Value
Publication number	US-10297664-B2
Application number	US-201715486351-A
Country	US
Kind code	B2
Filing date	Apr 13, 2017
Priority date	Apr 13, 2017
Publication date	May 21, 2019
Grant date	May 21, 2019

Abstract

A method of forming nanosheet and nanowire transistors includes the formation of alternating epitaxial layers of silicon germanium (SiGe) and silicon (Si), where the germanium content within respective layers of the silicon germanium is systemically varied in order to mediate the selective etching of these layers. The germanium content can be controlled such that voids created by removal of the silicon germanium have uniform dimensions, and the backfilling of such voids with gate dielectric and gate conductor layers proximate to silicon nanosheets or nanowires results in devices having a uniform effective gate length.

First claim

What is claimed is:

1. A method of fabricating a device, comprising:
forming a stack of alternating layers of epitaxial silicon germanium and epitaxial silicon over a semiconductor substrate;
patterning the stack of alternating layers of epitaxial silicon germanium and epitaxial silicon to form a fin; and
forming a sacrificial gate structure over the fin, wherein each successive layer of silicon germanium has a germanium content that is less than that of a previously-formed layer of silicon germanium.

2. The method of claim 1 , wherein the fin has a first width (W 1 ) measured orthogonal to a width of the sacrificial gate structure of 6 to 100 nm and a second width (W 2 ) measured parallel to the width of the sacrificial gate structure of 25 to 65 nm.

3. The method of claim 1 , wherein a first layer of silicon germanium is formed directly over the substrate.

4. The method of claim 1 , wherein a first layer of silicon germanium has a germanium content of 35 to 50 atomic percent.

5. The method of claim 1 , wherein each successive layer of silicon germanium has a germanium content that is 2 to 5 atomic percent less than that of the previously-formed layer of silicon germanium.

6. The method of claim 1 , wherein a topmost epitaxial layer in the stack comprises silicon germanium.

7. The method of claim 1 , wherein the layers of epitaxial silicon are undoped.

8. The method of claim 1 , further comprising forming sidewall spacers over sidewalls of the sacrificial gate structure and over a portion of a top surface of the fin.

9. The method of claim 8 , further comprising using the sidewall spacers and the sacrificial gate structure as an etch mask to etch exposed portions of the stack, wherein sidewalls of the stack after etching the exposed portions are inclined at an angle (α) relative to a direction orthogonal to a major surface of the substrate, where 0<α≤15°.

10. The method of claim 8 , further comprising removing the silicon germanium layers from under the sidewall spacers to form recessed regions.

11. The method of claim 10 , further comprising forming dielectric inner spacers within the recessed regions.

12. The method of claim 10 , wherein remaining portions of the silicon germanium layers have a substantially equal width.

13. The method of claim 1 , further comprising forming epitaxial source/drain regions laterally adjacent to the fin.

14. The method of claim 1 , further comprising removing the sacrificial gate structure from over the fin to form an opening and removing the epitaxial silicon germanium layers beneath the opening selective to the epitaxial silicon layers, wherein exposed portions of the epitaxial silicon layers define channel regions of the device.

15. The method of claim 14 , wherein the channel regions have a substantially constant width.

16. A method of fabricating a device, comprising:
forming a stack of alternating layers of epitaxial silicon germanium and epitaxial silicon over a semiconductor substrate, wherein each successive layer of silicon germanium has a germanium content that is 2 to 5 atomic percent less than that of a previously-formed layer of silicon germanium;
forming a sacrificial gate structure over the stack of alternating layers;
forming sidewall spacers over sidewalls of the sacrificial gate structure;
etching the stack of alternating layers using the sacrificial gate structure and the sidewall spacers as an etch mask to form a fin having tapered sidewalls; and
removing the silicon germanium layers from under the sidewall spacers to form recessed regions, wherein remaining portions of the silicon germanium layers have a substantially equal width.

17. The method of claim 16 , wherein each epitaxial layer of silicon is disposed between an underlying layer of epitaxial silicon germanium and an overlying layer of epitaxial silicon germanium.

18. The method of claim 16 , wherein the layers of epitaxial silicon germanium comprise 20 to 50 atomic percent germanium.

Assignees

• Globalfoundries Inc

Inventors

• Xie Ruilong

Classifications

• H10P50/642

  Chemical etching · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10P14/3252

  Alternating layers, e.g. superlattice · CPC title

• H10P14/3211

  Silicon, silicon germanium or germanium · CPC title

• H10P14/2905

  Silicon, silicon germanium or germanium · CPC title