Dielectric isolated SiGe fin on bulk substrate
US-9595599-B1 · Mar 14, 2017 · US
US10068920B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-10068920-B2 |
| Application number | US-201615098722-A |
| Country | US |
| Kind code | B2 |
| Filing date | Apr 14, 2016 |
| Priority date | Apr 14, 2016 |
| Publication date | Sep 4, 2018 |
| Grant date | Sep 4, 2018 |
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Relaxed silicon germanium fins are formed on a bulk silicon substrate through the lateral recrystallization of molten silicon germanium having high germanium content. Following formation of the silicon germanium fins, the silicon is selectively recessed. The resulting trenches are filled with electrically insulating material and then recessed down to the bottoms of the fins.
Opening claim text (preview).
What is claimed is: 1. A finned semiconductor structure comprising: a silicon substrate; a plurality of parallel silicon fins extending vertically from a top surface of the silicon substrate, wherein the plurality of parallel silicon fins are separated from each other by horizontal intervals, respectively; a dielectric layer on the silicon substrate and covering the silicon fins; and a plurality of relaxed parallel silicon germanium fins formed at the horizontal intervals, respectively, and directly contacting a top surface of the dielectric layer. 2. The finned semiconductor structure of claim 1 , wherein the plurality of relaxed parallel silicon germanium fins each have a composition of Si 1−x Ge x where x is between 0.50-0.99. 3. The finned semiconductor structure of claim 2 , wherein the plurality of relaxed parallel silicon germanium fins each are fully relaxed. 4. The finned semiconductor structure of claim 1 , wherein the plurality of relaxed parallel silicon germanium fins each have a composition of Si 1−x Ge x where x is 0.85 or greater. 5. The finned semiconductor structure of claim 1 , wherein the top surface of the dielectric layer is planar, and parallel trenches each are bounded by a respective one of the plurality of relaxed parallel silicon germanium fins and the top surface of the dielectric layer. 6. The finned semiconductor structure of claim 5 , further comprising a dielectric material within the parallel trenches. 7. The finned semiconductor structure of claim 6 , wherein the dielectric material is etched to a same level as the top surface of the dielectric layer. 8. The finned semiconductor structure of claim 7 , wherein the dielectric material and the dielectric layer form an electrically insulating layer. 9. The finned semiconductor structure of claim 8 , wherein the electrically insulating layer has a non-uniform thickness. 10. The finned semiconductor structure of claim 9 , wherein the plurality of relaxed parallel silicon germanium fins are boated above a surface of the plurality of parallel silicon fins. 11. The finned semiconductor structure of claim 10 , wherein the plurality of relaxed parallel silicon germanium fins are boated above a surface of the electrically insulating layer. 12. The finned semiconductor structure of claim 11 , wherein the plurality of relaxed parallel silicon germanium fins are located at a level different than that of the plurality of parallel silicon fins. 13. The finned semiconductor structure of claim 1 , wherein the plurality of relaxed parallel silicon germanium fins each have a height exceeding twenty-five nanometers. 14. The finned semiconductor structure of claim 1 , wherein the substrate is a bulk silicon substrate. 15. The finned semiconductor structure of claim 14 , wherein the plurality of relaxed parallel silicon germanium fins each are fully relaxed.
Thermal treatments, e.g. annealing or sintering · CPC title
into insulating materials · CPC title
the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz · CPC title
the material being a silicon oxide, e.g. SiO2 · CPC title
Amorphous · CPC title
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