System, apparatus and method for low overhead control transfer to alternate address space in a processor

Patent metadata

Field	Value
Publication number	US-10296338-B2
Application number	US-201615373668-A
Country	US
Kind code	B2
Filing date	Dec 9, 2016
Priority date	Dec 9, 2016
Publication date	May 21, 2019
Grant date	May 21, 2019

Abstract

In one embodiment, a processor includes: an accelerator associated with a first address space; a core associated with a second address space and including an alternate address space configuration register to store configuration information to enable the core to execute instructions from the first address space; and a control logic to configure the core based in part on information in the alternate address space configuration register. Other embodiments are described and claimed.

First claim

What is claimed is:

1. A processor comprising:
an accelerator to execute instructions, the accelerator associated with a first address space;
a core coupled to the accelerator, the core associated with a second address space and including an alternate address space configuration register to store configuration information to enable the core to execute instructions from the first address space, the alternate address space configuration register having a first field to store a first enable indicator to indicate that the core is to fetch a next instruction from the first address space, wherein the core is to execute a write instruction to store configuration information in the alternate address space configuration register and to thereafter jump to execution of code from the second address space; and
a control logic to configure the core based in part on the first enable indicator.

2. A processor comprising:
an accelerator to execute instructions, the accelerator associated with a first address space;
a core coupled to the accelerator, the core associated with a second address space and including an alternate address space configuration register to store configuration information to enable the core to execute instructions from the first address space, the alternate address space configuration register having a first field to store a first enable indicator to indicate that the core is to fetch a next instruction from the first address space;
a control logic to configure the core based in part on the first enable indicator; and
a first selection circuit having a first input port to receive a first instruction stream from the first address space and a second input port to receive a second instruction stream from the second address space, wherein the control logic is to cause the first selection circuit to provide the next instruction from the first input port based at least in part on the first enable indicator.

3. The processor of claim 1 , wherein the alternate address space configuration register further comprises a second field to store a second enable indicator to indicate that an address of the next instruction from the first address space is to be obtained from a first register of the core.

4. The processor of claim 3 , wherein the control logic, in response to a write instruction, is to write the configuration information into the alternate address space configuration register, and after the execution of the write instruction to cause a next instruction pointer to point to an address stored in the first register.

5. The processor of claim 1 , wherein the alternate address space configuration register further comprises a third field to store a third enable indicator to enable a flat addressing mode for the first address space.

6. The processor of claim 5 , wherein the control logic is to disable a translation lookaside buffer of the core based on the third enable indicator.

7. A processor comprising:
an accelerator to execute instructions, the accelerator associated with a first address space;
a core coupled to the accelerator, the core associated with a second address space and including an alternate address space configuration register to store configuration information to enable the core to execute instructions from the first address space, the alternate address space configuration register having a first field to store a first enable indicator to indicate that the core is to fetch a next instruction from the first address space;
a control logic to configure the core based in part on the first enable indicator; and
a selection circuit to receive an output of a retirement unit, the selection circuit having a first output port to couple to a cache memory of the core and a second output port to couple to a storage of the first address space.

8. The processor of claim 7 , wherein the control logic is to control the selection circuit to provide the output of the retirement unit to the storage of the first address space via the second output port based at least in part on another enable indicator stored in another field of the alternate address space configuration register.

9. The processor of claim 1 , further comprising a semiconductor die comprising the accelerator and the core.

10. The processor of claim 9 , wherein the core is of a first instruction set architecture (ISA) and the accelerator comprises a core of a second ISA.

11. The processor of claim 2 , further comprising a second selection circuit to receive an output of a retirement unit, the second selection circuit having a first output port to couple to a cache memory of the core and a second output port to couple to a storage of the first address space.

12. The processor of claim 2 , wherein the core is to execute a write instruction to store configuration information in the alternate address space configuration register and to thereafter jump to execution of code from the second address space.

13. The processor of claim 2 , further comprising a semiconductor die comprising the accelerator and the core.

14. The processor of claim 13 , wherein the core is of a first instruction set architecture (ISA) and the accelerator comprises a core of a second ISA.

15. The processor of claim 7 , further comprising a semiconductor die comprising the accelerator and the core.

16. The processor of claim 15 , wherein the core is of a first instruction set architecture (ISA) and the accelerator comprises a core of a second ISA.

Assignees

• Intel Corp

Inventors

• Boswell Brent R
• Nagasundaram Banu Meenakshi
• Abbott Michael D
• Dakshinamoorthy Srikanth
• Howard Jason M
• Fryman Joshua B

Classifications

• G06F9/3881

  Arrangements for communication of instructions and data · CPC title

• G06F9/3802

  Instruction prefetching · CPC title

• G06F9/30189

  according to execution mode, e.g. mode flag · CPC title

• G06F9/30101 Primary

  Special purpose registers · CPC title