Method and apparatus for dishonest hardware policies

Patent metadata

Field	Value
Publication number	US-8935775-B2
Application number	US-201213630592-A
Country	US
Kind code	B2
Filing date	Sep 28, 2012
Priority date	Jun 28, 2012
Publication date	Jan 13, 2015
Grant date	Jan 13, 2015

Abstract

A system implements dishonest policies for managing unauthorized access requests. The system includes memory management hardware to store a set of dishonest policy bits, each dishonest policy bit that is configured to a predetermined value indicating disallowed access for one of a set of memory ranges. When a processor receives an access request for a location in a memory range to which access is not allowed as indicated by a set dishonest policy bit, the processor returns a false indication according to a dishonest policy that the requested access has been performed.

First claim

What is claimed is:

1. An apparatus comprising:
memory management hardware to store a plurality of dishonest policy bits per memory range, each dishonest policy bit indicating disallowed access for a corresponding memory range and wherein a first dishonest policy bit when set is to specify that a write to the corresponding memory range is to be discarded and a load from the corresponding memory range is to return a random number, and a second dishonest policy bit when set is to specify that a write to the corresponding memory range is to be discarded and a load from the corresponding memory range is to return all zeros; and
a processor coupled to the memory management hardware, the processor including circuitry to receive an access request for a location in a memory range to which access is not allowed as indicated by a given one of the dishonest policy bits that is configured to a value, and to return a false indication according to a given dishonest policy corresponding to the given dishonest policy bit that the requested access has been performed.

2. The apparatus of claim 1 , wherein the set of dishonest policy bits are stored in a hardware permission table separate from a page table.

3. The apparatus of claim 1 , wherein the set of dishonest policy bits are stored in an extension of a page table, which is accessible by the processor for translation of virtual memory addresses.

4. The apparatus of claim 1 , wherein the set of dishonest policy bits are configurable by trusted software.

5. The apparatus of claim 1 , wherein the processor according to the given dishonest policy is to return, in response to a read request, a value that is not an actual content stored in the location in the one of the memory ranges.

6. The apparatus of claim 1 , wherein the processor according to the given dishonest policy is to discard a write value in response to a write request and return an acknowledgement to the write request.

7. The apparatus of claim 1 , wherein the processor is a given core in a multi-core processing system, and wherein the memory management hardware for the given core includes an ingress portion and an egress portion, the ingress portion specifying a first set of access permission for a first application that runs on other cores in the multi-core processing system and submits access requests to the given core, and the egress portion specifying a second set of access permission for a second application that runs on the given core and submits the access requests to the given core.

8. The apparatus of claim 1 , wherein the processor belongs to a core group of a plurality of cores in a multi-core processing system, the memory management hardware for the core group includes an ingress portion and an egress portion, the ingress portion specifying a first set of access permission for a first application that runs on another core group in the multi-core processing system and submits access requests to the core group, and the egress portion specifying a second set of access permission for a second application that runs on the core group and submits the access requests to the core group.

9. A method comprising:
receiving by a processor an access request for accessing a location in a memory range;
determining that the requested access is not allowed, wherein disallowed access for the memory range is indicated by a given one of a set of dishonest policy bits that is configured to a value for the memory range, wherein a first dishonest policy bit when set is to specify that a write to the corresponding memory range is to be discarded and a load from the corresponding memory range is to return a random number, and a second dishonest policy bit when set is to specify that a write to the corresponding memory range is to be discarded and a load from the corresponding memory range is to return all zeros; and
according to a dishonest policy corresponding to the given dishonest policy bit, returning a false indication that the requested access has been performed, wherein returning the false indication comprises:
returning, in response to a read request, a random number when the first dishonest policy bit is set, and
returning, in response to a read request, all zeros when the second dishonest policy bit is set.

10. The method of claim 9 , wherein the set of dishonest policy bits are stored in a hardware permission table separate from a page table.

11. The method of claim 9 , wherein the set of dishonest policy bits are stored in an extension of a page table, which is accessible by the processor for translation of virtual memory addresses.

12. The method of claim 9 , wherein the set of dishonest policy bits are configurable by trusted software.

13. The method of claim 9 , wherein returning the false indication further comprises:
returning same values in response to a first set of read requests received within a quasi-random time window; and
returning different values in response to a second set of read requests received in different quasi-random time windows.

14. The method of claim 9 , wherein returning the false indication further comprises:
returning, in response to a read request, a value in a predetermined order from a rotating table of values, which are periodically replaced with new random or pseudo-random values.

15. The method of claim 9 , wherein returning the false indication further comprises:
returning, in response to a read request, a value generated from a bloom filter which applies a probability function to previous writes that were made to the location in the memory range.

16. The method of claim 9 , wherein returning the false indication further comprises:
discarding a write value in response to a write request; and
returning an acknowledgement to the write request.

17. A system comprising:
memory to store code and data;
memory management hardware to store a plurality of dishonest policy bits per memory range, each dishonest policy bit indicating disallowed access for a corresponding memory range and wherein a first dishonest policy bit when set is to specify that a write to the corresponding memory range is to be discarded and a load from the corresponding memory range is to return a random number, and a second dishonest policy bit when set is to specify that a write to the corresponding memory range is to be discarded and a load from the corresponding memory range is to return all zeros; and
a processor coupled to the memory management hardware, the processor including circuitry to receive an access request for a location in a memory range to which access is not allowed as indicated by a given one of the dishonest policy bits that is configured to a value, and to return a false indication according to a given dishonest policy corresponding to the given dishonest policy bit that the requested access has been performed.

18. The system of claim 17 , wherein the set of dishonest policy bits are stored in a hardware permission table separate from a page table.

19. The system of claim 17 , wherein the set of dishonest policy bits are stored in an extension of a page table, which is accessible by the processor for translation of virtual memory addresses.

20. The system of claim 17 , wherein the set of dishonest policy bits are configurable by trusted software.

Assignees

• Fryman Joshua
• Carter Nicholas
• Knauerhase Robert
• Schoenberg Sebastian
• Agrawal Aditya
• Intel Corp

Inventors

• Fryman Joshua
• Carter Nicholas
• Knauerhase Robert
• Schoenberg Sebastian
• Agrawal Aditya

Classifications

• G06F12/00

  Accessing, addressing or allocating within memory systems or architectures (digital input from, or digital output to record carriers, e.g. to disk storage units, G06F3/06) · CPC title

• G06F12/14 Primary

  Protection against unauthorised use of memory {or access to memory} · CPC title

• G06F13/16

  for access to memory bus (G06F13/28 takes precedence) · CPC title

• G06F13/1668

  Details of memory controller · CPC title

• G06F12/1441 Primary

  for a range · CPC title