Adaptive pulse generation circuits for clocking pulse latches with minimum hold time

Patent metadata

Field	Value
Publication number	US-10291211-B2
Application number	US-201615259633-A
Country	US
Kind code	B2
Filing date	Sep 8, 2016
Priority date	Sep 8, 2016
Publication date	May 14, 2019
Grant date	May 14, 2019

Abstract

Adaptive pulse generation circuits for clocking pulse latches with minimum hold time are provided. In one aspect, an adaptive pulse generation circuit employs a dynamic XOR-based logic gate configured to provide a pulse generation signal based on an XOR-based function of data input and data output-based signals of a pulse latch. A pull-down keeper circuit is configured to pull the pulse generation signal to a ground voltage in response to the pulse generation signal being in an inactive state while the clock signal is in an active state. A logic circuit is configured to generate an adaptive pulse signal to clock a pulse latch in response to the pulse generation signal and the clock signal being in an active state. This configuration results in the pulse width of the adaptive pulse signal corresponding to the input-to-output delay of the pulse latch.

First claim

What is claimed is:

1. An adaptive pulse generation circuit for generating an adaptive pulse signal for a pulse latch, comprising:
a dynamic XOR-based logic gate, comprising:
a clock input configured to receive a clock signal;
a first input configured to receive a data input signal of the pulse latch;
a second input configured to receive a data output-based signal of the pulse latch; and
an output configured to:
provide a pulse generation signal in an active state in response to the clock signal being in an inactive state; and
provide the pulse generation signal in a state according to an XOR-based function of the data input signal and the data output-based signal in response to the clock signal being in an active state;

a pull-down keeper circuit configured to pull the pulse generation signal to a ground voltage in response to the pulse generation signal being in an inactive state and the clock signal being in the active state; and
a logic circuit configured to generate the adaptive pulse signal having a pulse width corresponding to an input-to-output delay of the pulse latch in response to the pulse generation signal and the clock signal being in the active state, wherein the logic circuit comprises:
an AND-based logic gate, comprising:
a first input configured to receive the clock signal;
a second input electrically coupled to the output of the dynamic XOR-based logic gate; and
an output configured to provide an inverted adaptive pulse signal; and

an inverter, comprising:
an input electrically coupled to the output of the AND-based logic gate; and
an output configured to provide the adaptive pulse signal.

2. The adaptive pulse generation circuit of claim 1 , wherein:
the data output-based signal has a state that is the same as a state of a data output signal of the pulse latch;
the data output signal is provided from a data output of the pulse latch; and
the data output-based signal is provided from a data pulse output of the pulse latch different from the data output.

3. The adaptive pulse generation circuit of claim 1 , wherein the output of the dynamic XOR-based logic gate is configured to provide the pulse generation signal in the active state by the dynamic XOR-based logic gate being configured to pre-charge the pulse generation signal to a source voltage in response to the clock signal being in the inactive state.

4. The adaptive pulse generation circuit of claim 1 , wherein the dynamic XOR-based logic gate further comprises:
a first P-type metal oxide semiconductor (MOS) (PMOS) transistor, comprising:
a source electrically coupled to a supply voltage source;
a gate electrically coupled to the clock input; and
a drain electrically coupled to the output of the dynamic XOR-based logic gate;

a first N-type MOS (NMOS) transistor, comprising:
a source electrically coupled to a ground voltage source;
a gate electrically coupled to the clock input; and
a drain;

a second NMOS transistor, comprising:
a source electrically coupled to the drain of the first NMOS transistor;
a gate electrically coupled to the first input of the dynamic XOR-based logic gate; and
a drain; and

a third NMOS transistor, comprising:
a source electrically coupled to the drain of the second NMOS transistor;
a gate electrically coupled to the second input of the dynamic XOR-based logic gate; and
a drain electrically coupled to the output of the dynamic XOR-based logic gate.

5. The adaptive pulse generation circuit of claim 4 , wherein the dynamic XOR-based logic gate further comprises:
a fourth NMOS transistor, comprising:
a source electrically coupled to the drain of the first NMOS transistor;
a gate configured to receive an inverted data input signal comprising a logical inverse of the data input signal; and
a drain; and

a fifth NMOS transistor, comprising:
a source electrically coupled to the drain of the fourth NMOS transistor;
a gate configured to receive an inverted data output-based signal comprising a logical inverse of the data output-based signal; and
a drain electrically coupled to the output of the dynamic XOR-based logic gate.

6. The adaptive pulse generation circuit of claim 4 , wherein the pull-down keeper circuit comprises:
an NMOS transistor, comprising:
a source electrically coupled to the drain of the first NMOS transistor in the dynamic XOR-based logic gate;
a gate; and
a drain electrically coupled to the output of the dynamic XOR-based logic gate; and

an inverter, comprising:
an input electrically coupled to the output of the dynamic XOR-based logic gate; and
an output electrically coupled to the gate of the NMOS transistor of the pull-down keeper circuit.

7. The adaptive pulse generation circuit of claim 1 integrated into an integrated circuit (IC).

8. The adaptive pulse generation circuit of claim 1 integrated into a device selected from the group consisting of: a set top box; an entertainment unit; a navigation device; a communications device; a fixed location data unit; a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cellular phone; a smart phone; a session initiation protocol (SIP) phone; a tablet; a phablet; a server; a computer; a portable computer; a mobile computing device; a wearable computing device; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; an automobile; a vehicle component; avionics systems; a drone; and a multicopter.

9. An adaptive pulse generation circuit for generating an adaptive pulse signal for a pulse latch, comprising:
a means for receiving a clock signal;
a means for receiving a data input signal of the pulse latch;
a means for receiving a data output-based signal of the pulse latch;
a means for providing a pulse generation signal in an active state in response to the clock signal being in an inactive state;
a means for providing the pulse generation signal in a state according to an XOR-based function of the data input signal and the data output-based signal in response to the clock signal being in an active state;
a means for pulling the pulse generation signal to a ground voltage in response to the pulse generation signal being in an inactive state and the clock signal being in the active state; and
a means for generating the adaptive pulse signal having a pulse width corresponding to an input-to-output delay of the pulse latch in response to the pulse generation signal and the clock signal being in the active state, wherein the means for generating the adaptive pulse signal comprises:
a means for generating an inverted adaptive pulse signal by performing a NAND-based logic function on the clock signal and the pulse generation signal; and
a means for inverting the inverted adaptive pulse signal to generate the adaptive pulse signal.

10. The adaptive pulse generation circuit of claim 9 , wherein the means for providing the pulse generation signal in the active state comprises a means for pre-charging the pulse generation signal to a source voltage in response to the clock signal being in the inactive state.

11. A digital logic circuit, comprising:
a plurality of pulse latches, wherein each pulse latch of the plurality of pulse latches comprises:
a data input configured to receive a data input signal;
a pulse input configured to receive a corresponding adaptive pulse signal; and
a data pulse output configured to provide a data output-based signal; and

a plurality

Assignees

• Qualcomm Technologies Inc
• Yonsei Univ Univ Industry Foundation
• Qualcomm Inc

Inventors

• Song Stanley Seungchul
• Jung Seong-Ook
• Jeong Hanwool
• Oh Tae Woo
• Nallapati Giridhar
• Chidambaram Periannan

Classifications

• H03K3/012

  Modifications of generator to improve response time or to decrease power consumption · CPC title

• H03K3/037

  Bistable circuits · CPC title

• H03K3/017

  Adjustment of width or dutycycle of pulses (pulse width modulation H03K7/08 {; to maintain energy constant H03K3/015}) · CPC title

• H03K3/356104 Primary

  using complementary field-effect transistors (H03K3/35625 takes precedence) · CPC title

• H03K3/0375

  provided with means for increasing reliability; for protection; for ensuring a predetermined initial state when the supply voltage has been applied; for storing the actual state when the supply voltage fails (digital storage cells each combining volatile and non-volatile storage properties G11C14/00) · CPC title