Memory cells having a number of conductive diffusion barrier materials and manufacturing methods

Patent metadata

Field	Value
Publication number	US-10290800-B2
Application number	US-201715635945-A
Country	US
Kind code	B2
Filing date	Jun 28, 2017
Priority date	Jul 26, 2013
Publication date	May 14, 2019
Grant date	May 14, 2019

Abstract

Memory cells having a select device material located between a first electrode and a second electrode, a memory element located between the second electrode and a third electrode, and a number of conductive diffusion barrier materials located between a first portion of the memory element and a second portion of the memory element. Memory cells having a select device comprising a select device material located between a first electrode and a second electrode, a memory element located between the second electrode and a third electrode, and a number of conductive diffusion barrier materials located between a first portion of the select device and a second portion of the select device. Manufacturing methods are also described.

First claim

What is claimed is:

1. A memory cell, comprising:
a programmable memory element located between a first electrode and a second electrode;
wherein the programmable memory element comprises at least a first programmable memory element portion and a second programmable memory element portion; and
a conductive diffusion barrier material located between the first programmable memory element portion and the second programmable memory element portion of the programmable memory element.

2. The memory cell of claim 1 , wherein the first programmable memory element portion and the second programmable memory element portion each comprise a chalcogenide material.

3. The memory cell of claim 2 , wherein the chalcogenide material is a resistance variable material.

4. The memory cell of claim 2 , wherein the chalcogenide material is a phase change material.

5. The memory cell of claim 2 , wherein a composition of the chalcogenide material of the first programmable memory element portion is different than a composition of the chalcogenide material of the second programmable memory element portion.

6. The memory cell of claim 1 , wherein a thickness of the chalcogenide material of the first programmable memory element portion is different than a thickness of the chalcogenide material of the second programmable memory element portion.

7. The memory cell of claim 1 , wherein a thickness of the chalcogenide material of the first programmable memory element portion and a thickness of the chalcogenide material of the second programmable memory element portion is not greater than 10 nanometers.

8. The memory cell of claim 1 , wherein the programmable memory element comprises:
at least a third programmable memory element portion; and
a conductive diffusion barrier material located between the second programmable memory element portion and the third programmable memory element portion of the programmable memory element.

9. The memory cell of claim 8 , wherein a thickness of the conductive diffusion barrier material located between the second programmable memory element portion and the third programmable memory element portion and a thickness of the conductive diffusion barrier material located between the first programmable memory element portion and the second programmable memory element portion is not greater than 50 angstroms.

10. The memory cell of claim 8 , wherein the conductive diffusion barrier material located between the second programmable memory element portion and the third programmable memory element portion and the conductive diffusion barrier material located between the first programmable memory element portion and the second programmable memory element portion have different thicknesses.

11. The memory cell of claim 8 , wherein the conductive diffusion barrier material located between the second programmable memory element portion and the third programmable memory element portion and the conductive diffusion barrier material located between the first programmable memory element portion and the second programmable memory element portion have different compositions.

12. The memory cell of claim 11 , wherein the conductive diffusion barrier material located between the second programmable memory element portion and the third programmable memory element portion and the conductive diffusion barrier material located between the first programmable memory element portion and the second programmable memory element portion comprise at least one of carbon and carbon nitride.

13. The memory cell of claim 1 , further comprising a select device material located between the second electrode and a third electrode.

14. The memory cell of claim 13 , wherein the select device material comprises a first portion and a second portion, and wherein a conductive diffusion barrier material is located between the first portion and the second portion.

15. The memory cell of claim 13 , wherein the select device material comprises a chalcogenide material.

16. The memory cell of claim 15 , wherein a composition of the select device material is different than a composition of the programmable memory element portions.

17. A method of forming a memory cell, comprising:
forming a programmable memory element located between a first electrode and a second electrode;
wherein forming the programmable memory element comprises forming at least a first programmable memory element portion and a second programmable memory element portion; and
forming a conductive diffusion barrier material located between the first programmable memory element portion and the second programmable memory element portion of the programmable memory element.

18. The method of claim 17 , wherein the first programmable memory element portion and the second programmable memory element portion each comprise a chalcogenide material.

19. The method of claim 17 , wherein forming the programmable memory element comprises:
forming at least a third programmable memory element portion; and
forming a conductive diffusion barrier material located between the second programmable memory element portion and the third programmable memory element portion of the programmable memory element.

20. The method of claim 17 , wherein the method includes forming a select device material between the second electrode and a third electrode.

21. A memory cell, comprising:
a programmable memory element located between a first electrode and a second electrode;
wherein the programmable memory element comprises at least two programmable chalcogenide portions; and
wherein a conductive diffusion barrier material is interleaved with the at least two programmable chalcogenide portions such that each of the conductive diffusion barrier materials is separated by at least one programmable chalcogenide portion.

Assignees

• Micron Technology Inc

Inventors

• Gotti Andrea
• Gealy F Daniel
• Colombo Davide

Classifications

• H01L45/1233

  Electricity · mapped topic

• H01L45/12 Primary

  Electricity · mapped topic

• H01L45/144

  Electricity · mapped topic

• H01L45/1608

  Electricity · mapped topic

• H01L45/06

  Electricity · mapped topic