Three-dimensional non-volatile memory device having a silicide source line and method of making thereof

Patent metadata

Field	Value
Publication number	US-9559117-B2
Application number	US-201514734254-A
Country	US
Kind code	B2
Filing date	Jun 9, 2015
Priority date	Jun 17, 2014
Publication date	Jan 31, 2017
Grant date	Jan 31, 2017

Abstract

A memory device and a method of making a memory device that includes a stack of alternating layers of a first material and a second material different from the first material over a substrate, where the layers of the second material form a plurality of conductive control gate electrodes. A plurality of NAND memory strings extend through the stack, where each NAND memory string includes a semiconductor channel which contains at least a first portion which extends substantially perpendicular to a major surface of the substrate and at least one memory film located between the semiconductor channel and the plurality of conductive control gate electrodes. A source line including a metal silicide material extends through the stack.

First claim

What is claimed is:

1. A memory device, comprising:
a stack of alternating layers of a first material and a second material different from the first material over a substrate, wherein the layers of the second material form a plurality of conductive control gate electrodes;
a plurality of NAND memory strings extending through the stack, wherein each NAND memory string comprises:
a semiconductor channel which contains at least a first portion which extends substantially perpendicular to a major surface of the substrate; and
at least one memory film located between the semiconductor channel and the plurality of conductive control gate electrodes;

a source line comprising a metal silicide material which extends though the stack;
a source region located in a second portion of the semiconductor channel extending substantially parallel to the major surface of the substrate; and
an insulating material is located between the source line and the plurality of conductive control gate electrodes.

2. The device of claim 1 , wherein the source line electrically contacts the source region.

3. The device of claim 1 , wherein the source line comprises at least one of tungsten silicide, titanium silicide and nickel silicide.

4. The device of claim 1 , wherein the source line comprises a metal material core extending through the stack adjacent to the metal silicide material.

5. The device of claim 4 , wherein the metal material core comprises at least one of tungsten, titanium and nickel.

6. The device of claim 1 , further comprising a silicon layer located between the metal silicide material of the source line and the insulating material.

7. The device of claim 1 , wherein the source line comprises a lower portion proximate to the source region and an upper portion distal to the source region, wherein a width of the source line in the upper portion is greater than a width of the source line in the lower portion.

8. The device of claim 1 , further comprising:
a metal fill material comprising a metal or metal alloy material that is different than the material of the source line, wherein at least one of:
(i) the metal fill material is located between the source region and the source line; and
(ii) the metal fill material is located above the source line in the stack, such that the source line is located between the source region and the metal fill material.

9. The device of claim 8 , wherein the metal fill material comprises a metal or metal alloy comprising at least one of copper and aluminum.

10. The device of claim 1 , wherein
the substrate comprises a silicon substrate;
the plurality of NAND memory strings comprises an array of monolithic three-dimensional NAND strings over the silicon substrate;
at least one memory cell in a first device level of the array of monolithic three-dimensional NAND strings is located over another memory cell in a second device level of the array of monolithic three-dimensional NAND strings;
the silicon substrate contains an integrated circuit comprising a driver circuit for the memory device; and
the at least one memory film comprises a plurality of charge storage elements, each charge storage element located adjacent to the first portion of the semiconductor channel; and
the plurality of conductive control gate electrodes have a strip shape extending substantially parallel to the top surface of the substrate, the plurality of control gate electrodes comprise at least a first control gate electrode located in the first device level and a second control gate electrode located in the second device level.

Assignees

• Sandisk Technologies Inc
• Sandisk Technologies Llc

Inventors

• Pachamuthu Jayavel
• Dong Yingda
• Alsmeier Johann

Classifications

• H10P14/3456

  Polycrystalline · CPC title

• H10P14/3454

  Amorphous · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10W20/4446

  Refractory-metal alloys · CPC title

• H10W20/4424

  Copper alloys · CPC title