Chip resistor and method of making the same

Patent metadata

Field	Value
Publication number	US-10290402-B2
Application number	US-201715457423-A
Country	US
Kind code	B2
Filing date	Mar 13, 2017
Priority date	Mar 15, 2016
Publication date	May 14, 2019
Grant date	May 14, 2019

Abstract

The present invention provides a chip resistor and a method of making the same for alleviating stress resulted from thermal expansion difference and thus suppressing cracks. A chip resistor includes: a substrate, having a carrying surface and a mounting surface facing away from each other; a pair of upper electrodes, disposed at two ends of the carrying surface; a resistor, disposed on the carrying surface and between the pair of upper electrodes, and electrically connected to the pair of upper electrodes; a stress relaxation layer having flexibility and formed on the mounting surface of the substrate; a metal thin film layer, formed on a surface of the stress relaxation layer opposite to the substrate; a side electrode for electrically connecting the upper electrodes and the metal thin film layer; and a plating layer covering the side electrode and the metal thin film layer.

First claim

What is claimed is:

1. A chip resistor, comprising:
a substrate having a carrying surface and a mounting surface facing away from each other;
a pair of upper electrodes disposed at two ends of the carrying surface of the substrate;
a resistor mounted on the carrying surface of the substrate, and between the pair of upper electrodes, the resistor being electrically connected to the pair of upper electrodes;
a stress relaxation layer having flexibility and formed on the mounting surface of the substrate;
a metal thin film layer formed on a surface of the stress relaxation layer opposite to the substrate and having a pair of regions spaced apart in a first direction;
a pair of side electrodes for electrically connecting the pair of upper electrodes and the pair of regions of the metal thin film layer, and a portion of the metal thin film layer is covered by one of the side electrodes; and
a plating layer covering the side electrode and the metal thin film layer.

2. The chip resistor of claim 1 , wherein the stress relaxation layer comprises silicone resin or epoxy resin.

3. The chip resistor of claim 1 , wherein the stress relaxation layer comprises conductive resin.

4. The chip resistor of claim 1 , wherein the stress relaxation layer is formed on all of the mounting surface of the substrate.

5. The chip resistor of claim 1 , wherein the stress relaxation layer comprises a pair of regions spaced apart from each other in the first direction and formed respectively at two ends of the mounting surface of the substrate.

6. The chip resistor of claim 5 , wherein end surfaces of each of the regions of the stress relaxation layer, facing each other in the first direction, are exposed by each of the regions of the metal thin film layer, and each of the regions of the metal thin film layer covers a part of each of the regions of the stress relaxation layer.

7. The chip resistor of claim 5 , wherein end surfaces of each of the regions of the stress relaxation layer, facing each other in the first direction, are covered by each of the regions of the metal thin film layer.

8. The chip resistor of claim 1 , wherein the metal thin film layer comprises Ni—Cr alloy.

9. The chip resistor of claim 1 , wherein the metal thin film layer comprises a sputtered layer.

10. The chip resistor of claim 9 , wherein the side electrode comprises a second sputtered layer formed on a side surface of the substrate between the carrying surface and the mounting surface of the substrate; wherein the sputtered layer and the second sputtered layer are integrally formed.

11. The chip resistor of claim 1 , wherein the side electrode comprises:
a portion disposed on a side surface of the substrate between the carrying surface and the mounting surface of the substrate; and
a portion overlapping with the carrying surface and the mounting surface in a thickness direction of the substrate.

12. The chip resistor of claim 1 , wherein the side electrode comprises Ni—Cr alloy.

13. The chip resistor of claim 1 , wherein the plating layer comprises a Ni plating layer and a Sn plating layer.

14. The chip resistor of claim 1 , wherein a thickness of the stress relaxation layer is 10-50 μm.

15. The chip resistor of claim 1 , wherein the substrate is an electrical insulator.

16. The chip resistor of claim 15 , wherein the substrate comprises alumina.

17. The chip resistor of claim 1 , wherein the resistor is of a serpentine shape as viewed from a top view.

18. The chip resistor of claim 1 , wherein the resistor comprises RuO2 or Ag—Pd alloy.

19. The chip resistor of claim 1 , wherein the resistor has a trimming groove penetrating in a thickness direction.

20. The chip resistor of claim 1 , further comprising a protective film covering the resistor and a part of the upper electrode.

21. The chip resistor of claim 20 , wherein the protective film has a lower protective film and an upper protective film.

22. The chip resistor of claim 21 , wherein the lower protective film comprises glass.

23. The chip resistor of claim 21 , wherein the upper protective film comprises epoxy resin.

24. A method of making a chip resistor, comprising:
preparing a sheet-like substrate with a carrying surface and a mounting surface facing away from each other, and forming a pair of upper electrodes spaced apart from one another on the carrying surface of the sheet-like substrate;
mounting a resistor electrically connected to the upper electrodes in a region of the carrying surface of the sheet-like substrate sandwiched between the pair of upper electrodes;
forming a stress relaxation layer having flexibility on the mounting surface;
forming a metal thin film layer having a pair of regions on a surface of the stress relaxation layer opposite to the sheet-like substrate;
dividing the sheet-like substrate into a plurality of strip-shaped substrates with short sides in a direction in which the pair of upper electrodes are separated;
forming a pair of side electrodes for electrically connecting the pair of upper electrodes and the pair of regions of the metal thin film layer, on a side surface along two ends in a longitudinal direction of the strip-shaped substrate, the mounting surface, and the mounting surface; and
forming a plating layer covering the side electrodes and the metal thin film layer.

25. The method of making a chip resistor of claim 24 , wherein forming the metal thin film layer is by physical vapor deposition.

26. The method of making a chip resistor of claim 25 , wherein the physical vapor deposition is sputtering.

27. The method of making a chip resistor of claim 24 , wherein the resistor is mounted by printing, or physical vapor deposition and photolithography.

28. The method of making a chip resistor of claim 24 , further comprising dividing the strip-shaped substrate into a plurality of pieces before forming the plating layer.

29. The method of making a chip resistor of claim 24 , further comprising forming a trimming groove through the resistor.

30. The method of making a chip resistor of claim 24 , further comprising forming a protective film covering the resistor and a portion of the upper electrode.

31. A chip resistor, comprising:
a substrate having a carrying surface and a mounting surface facing away from each other;
a pair of upper electrodes disposed at two ends of the carrying surface of the substrate;
a resistor mounted on the carrying surface of the substrate, and between the pair of upper electrodes, the resistor being electrically connected to the pair of upper electrodes;
a stress relaxation layer with flexibility formed on the mounting surface of the substrate, and having a pair of regions spaced apart from each other in the first direction and formed respectively at two ends of the mounting surface of the substrate;
a metal thin film layer formed on a surface of the stress relaxation layer opposite to the substrate and having a pair of regions spaced apart in a first direction;
a pair of side electrodes for electrically connecting the pair of upper electrodes and the pair of regions of the metal thin film layer; and
a plating layer covering the side electrode and the metal thin film layer, wherein end surfaces of each of the regions of the stress relaxation layer, facing each other in the first direction, are covered b

Assignees

• Rohm Co Ltd

Inventors

• Yoneda Masaki

Classifications

• H01C1/142 Primary

  the terminals or tapping points being coated on the resistive element · CPC title

• H01C17/242

  by laser · CPC title

• H01C17/288

  by thin film techniques · CPC title

• H01C1/148

  the terminals embracing or surrounding the resistive element (H01C1/142 takes precedence) · CPC title

• H01C17/006

  adapted for manufacturing resistor chips · CPC title