System, method and computer product for enhanced decoupling capacitor implementation

Patent metadata

Field	Value
Publication number	US-10289790-B2
Application number	US-201715622625-A
Country	US
Kind code	B2
Filing date	Jun 14, 2017
Priority date	Jun 14, 2017
Publication date	May 14, 2019
Grant date	May 14, 2019

Abstract

A method for designing an integrated circuit die, the method including generating a first layout for the die which includes at least one decap; and performing a post-processing decap insertion operation to add at least one additional decap in excess of the at least one decap, the operation including: for at least a portion of the first layout, identifying at least some of whichever locations in at least the portion have positive slack, as “candidate” locations; and inserting at least one additional decap at at least one respective location from among the “candidate” locations.

First claim

The invention claimed is:

1. A method for designing an integrated circuit die, the method including:
generating a first layout for the die which includes at least one decap cell; and
performing a post-processing decap insertion operation to add to said layout at least one additional decap cell in excess of said at least one decap cell, the operation including:
for at least a portion of said first layout which comprises locations of dcap cells having net crossings with positive slack, identifying at least some of said net crossings at the locations in said at least said portion which have positive slack, as “candidate” locations; and
inserting at least one additional decap cell at this one location respectively, from among said “candidate” location,

thereby to increase the intrinsic-cap value of decap cells, in said layout, and consequently in integrated circuits produced according to said layout,
wherein said post-processing decap insertion operation ensures critical/sensitive timing nets are not harmed so as to avoid re-routing that changes signal delay value, by refraining from replacing filler cells, which are associated with said crossings with critical/sensitive timing nets, with decap cells.

2. The method according to claim 1 wherein timing requirements are defined for the die and wherein the first layout for the die meets all of said timing requirements.

3. The method according to claim 1 wherein said at least a portion comprises the entire first layout.

4. The method according to claim 1 wherein within at least a portion of the die, said inserting at least one additional decap cell occurs repeatedly, in descending order of slack.

5. The method according to claim 4 wherein within the entire die, said inserting occurs repeatedly, in descending order of slack.

6. The method according to claim 1 wherein the first layout includes a set of filler locations including at least one filler location and wherein at least some filler locations in said set have METAL-1 signal crossing signal or clock nets, and wherein said identifying comprises identifying at least some of said filler locations in said set which have METAL-1 signal crosses.

7. The method according to claim 6 wherein said identifying comprises identifying, for at least said portion of said first layout for the die, only filler locations in at least said portion which have Metal-1 signal nets' crosses with positive timing slack, as “candidate” locations; and replacing at least one of said “candidate” locations with at least one decap respectively.

8. The method according to claim 1 wherein said portion comprises a set of filter locations and wherein all filler locations in said set whose nets have positive slack, are identified as “candidate” locations.

9. The method according to claim 1 wherein a capacitance value is defined for each of said decap cells, and wherein, within at least a portion of the die, said inserting occurs repeatedly until a stop-criterion is reached, the stop-criterion comprising: a sum of said capacitance values, over all dcaps inserted in said inserting, has reached a predetermined total capacitance.

10. The method according to claim 1 wherein the first layout includes a set of filler locations including at least one filler location and wherein for at least one filler location F in said set the method determines whether or not there is a metal-1 routing over the filler location F, the method also comprising a replacing operation, in which at least one filler location F′, in which the method has determined that there is no metal-1 routing over the filler location F′, is replaced by a decap.

11. The method according to claim 10 wherein all filler locations in said set are checked to determine whether or not there is metal-1 routing over each of the filler locations in said set.

12. The method according to claim 10 wherein a necessary condition for performing said replacing operation at an individual filler location is that there is no metal-1 routing over the individual filler location.

13. The method according to claim 1 wherein the die includes Metal-1 net segments with positive timing slack, the method also comprising:
identifying said Metal-1 net segments with positive timing,
forcing at least one Filler to Decap swap that causes a DRC/Net Short and
re-routing at least one Metal-1 net that is shorting to alleviate the signal shorts in a metal scheme higher than metal-1.

14. The method according to claim 1 wherein the first layout includes a set of filler locations including at least one filler location and wherein some of the set's filler location/s have nets crossings with positive slack and wherein said identifying comprises identifying at least some of said filler location/s which have nets with positive slack, as “candidate” locations.

15. The method according to claim 1 wherein a final optimization of dcap cell placement, including identifying available free areas and populating them with capacitors, takes place after closure of timing.

16. The method according to claim 15 wherein at least one Filler to decap cell swap which violates timing considerations is/are aborted.

17. The method according to claim 16 wherein all Filler to decap cell swaps which violate timing considerations are aborted.

18. The method according to claim 1 and also comprising recording, for at least one Filler location which has Metal-1 routing over the Filler, the timing condition of the nets that are routed in Metal-1 over the area occupied by the Filler cell and prioritizing filler locations for upcoming swap of these filler cells for decap cells, where High-priority timing condition comprises the filler cell having the smallest, yet at least Delta greater than zero, positive slack value and wherein swapping of a second filler cell does not take place if a predetermined stopping criterion is reached after a first filler cell with a positive slack value v_small has been swapped but before the second filler cell with a slack value v_2>v_small has been swapped.

19. The method according to claim 1 wherein Metal-1 crossings are checked including analyzing their timing and are marked “relevant” for route modification due to having positive slack or irrelevant if they do not have positive slack.

20. The method according to claim 1 wherein said locations comprise filler spaces.

21. The method according to claim 1 and also comprising producing at least one integrated circuit according to said layout.

22. A system for designing an integrated circuit die, the system including:
at least one processor configured for generating a first layout for the die which includes at least one decap cell; and
performing a post-processing decap insertion operation to add to said layout at least one additional decap cell in excess of said at least one decap cell, the operation including:
for at least a portion of said first layout which comprises locations of dcap cells having net crossings with positive slack, identifying at least some of said net crossings at the locations in said at least said portion which have positive slack, as “candidate” locations; and
inserting at least one additional decap cell at this one location respectively, from among said “candidate” location,

thereby to increase the intrinsic-cap value of decap cells, in said layout, and consequently in integrated circuits produced according to said layout,
wherein said post-processing decap insertion operation ensures critical/sensitive timing ne

Assignees

• Nuvoton Technology Corp

Inventors

• Heilprin Aryeh
• Diaz Rafael Eliezer
• Sharlin Arnon

Classifications

• G06F30/39 Primary

  Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347) · CPC title

• G06F2119/06

  Power analysis or power optimisation · CPC title

• G06F2111/04

  Constraint-based CAD · CPC title

• G06F30/367

  Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods · CPC title

• G06F30/3312

  Timing analysis · CPC title